arch: powerpc: Move CONFIG_FSL_ELBC to Kconfig

Enable ELBC from Kconfig.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 83df73369805aa259ab25b9fa171e3eb0b164917..c06a4db8fc3ab9ecce9577c072ab1c82bd0b4420 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -455,6 +455,7 @@ config ARCH_MPC8536
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_MPC8540
        bool
@@ -478,6 +479,7 @@ config ARCH_MPC8544
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_MPC8548
        bool
@@ -524,6 +526,7 @@ config ARCH_MPC8569
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
+       select FSL_ELBC
 
 config ARCH_MPC8572
        bool
@@ -538,6 +541,7 @@ config ARCH_MPC8572
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1010
        bool
@@ -572,6 +576,7 @@ config ARCH_P1011
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1020
        bool
@@ -585,6 +590,7 @@ config ARCH_P1020
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1021
        bool
@@ -598,6 +604,7 @@ config ARCH_P1021
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1022
        bool
@@ -613,6 +620,7 @@ config ARCH_P1022
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1023
        bool
@@ -624,6 +632,7 @@ config ARCH_P1023
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select FSL_ELBC
 
 config ARCH_P1024
        bool
@@ -637,6 +646,7 @@ config ARCH_P1024
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P1025
        bool
@@ -650,6 +660,7 @@ config ARCH_P1025
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P2020
        bool
@@ -664,6 +675,7 @@ config ARCH_P2020
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_2
        select SYS_PPC_E500_USE_DEBUG_TLB
+       select FSL_ELBC
 
 config ARCH_P2041
        bool
@@ -685,6 +697,7 @@ config ARCH_P2041
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select FSL_ELBC
 
 config ARCH_P3041
        bool
@@ -708,6 +721,7 @@ config ARCH_P3041
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select FSL_ELBC
 
 config ARCH_P4080
        bool
@@ -742,6 +756,7 @@ config ARCH_P4080
        select SYS_FSL_QORIQ_CHASSIS1
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
+       select FSL_ELBC
 
 config ARCH_P5020
        bool
@@ -762,6 +777,7 @@ config ARCH_P5020
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_PPC64
+       select FSL_ELBC
 
 config ARCH_P5040
        bool
@@ -782,6 +798,7 @@ config ARCH_P5040
        select SYS_FSL_SEC_BE
        select SYS_FSL_SEC_COMPAT_4
        select SYS_PPC64
+       select FSL_ELBC
 
 config ARCH_QEMU_E500
        bool
@@ -1277,6 +1294,9 @@ config SYS_PPC_E500_USE_DEBUG_TLB
 config FSL_IFC
        bool
 
+config FSL_ELBC
+       bool
+
 config SYS_PPC_E500_DEBUG_TLB
        int "Temporary TLB entry for external debugger"
        depends on SYS_PPC_E500_USE_DEBUG_TLB

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9bfaa4bfc2aa67e17aae1ad96034585964893054..8c42d72f6a486af429fbd74413a898d757be2f5f 100644 (file)
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -37,7 +37,6 @@
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #endif
 
-#define CONFIG_FSL_ELBC                1       /* Has Enhanced localbus controller */
 #define CONFIG_PCI1            1       /* Enable PCI controller 1 */
 #define CONFIG_PCIE1           1       /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2           1       /* PCIE controller 2 (slot 2) */

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 01be54be2f96fc3516fde11b444a30987c0696dc..baee4a06e05259247885586d65e98fbbb4e1c85c 100644 (file)
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -10,8 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_FSL_ELBC                1       /* Has Enhance localbus controller */
-
 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1                   /* SRIO port 1 */
 

diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index 5ca01e847035a37ce7e996c07ad4b151362bb54a..d7b136615f5180d27707b83a8feb76c15e027e01 100644 (file)
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -28,7 +28,6 @@
 /* High Level Configuration Options */
 #define CONFIG_MP              1       /* support multiple processors */
 
-#define CONFIG_FSL_ELBC                1       /* Has Enhanced localbus controller */
 #define CONFIG_PCIE1           1       /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2           1       /* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3           1       /* PCIE controller 3 (ULI bridge) */

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 1d219a79e2c59e49f8b55715653300f96f16df33..70dcd9b321f03edb1813da1d4a38841949478070 100644 (file)
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -96,7 +96,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_PCIE1                   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2                   /* PCIE controller 2 (slot 2) */
 #define CONFIG_PCIE3                   /* PCIE controller 3 (ULI bridge) */

diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index 1ab54123ff904e2537d8a52b76ee0fdbf3be6ddb..7b10625b54ade2a3b2d1d96a3a2f65dd36767f93 100644 (file)
--- a/include/configs/P1023RDB.h
+++ b/include/configs/P1023RDB.h
@@ -25,7 +25,6 @@
 /* High Level Configuration Options */
 #define CONFIG_MP              /* support multiple processors */
 
-#define CONFIG_FSL_ELBC                /* Has Enhanced localbus controller */
 #define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
 #define CONFIG_PCIE1           /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2           /* PCIE controller 2 (slot 2) */

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index ac579b69b463f3fbd8355c96cef6c38ef262dbaa..e22b1f5afc30ff4b4861f03a8a8e5d8e00bb454a 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -41,7 +41,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */

diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
index a0255dcb52be32e0ce9d22332f439ca62a650919..a9b7a5aba9a4e0be3fc60ca06835f80aaf552ed9 100644 (file)
--- a/include/configs/UCP1020.h
+++ b/include/configs/UCP1020.h
@@ -14,7 +14,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */

diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h
index d236f3a0200ab0ac36587e7dd2a3ff184a742990..7c6fd741d369fa559cae57f36c7c78176d545231 100644 (file)
--- a/include/configs/controlcenterd.h
+++ b/include/configs/controlcenterd.h
@@ -137,7 +137,6 @@
 /*
  * Local Bus Definitions
  */
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 
 #define CONFIG_SYS_ELBC_BASE           0xe0000000
 #ifdef CONFIG_PHYS_64BIT

diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 7a3de3160694dc7a873dcd2beee97a66d6cb8d8d..3ca30cbb71c713d9c9b1311b2801315db5030eab 100644 (file)
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -59,7 +59,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_FSL_CAAM                        /* Enable SEC/CAAM */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */

diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h
index 71a55d8ccd2cf289beeba2cbac09406dd83bdd20..e98682c1201d2426730596d5a256624253622c19 100644 (file)
--- a/include/configs/cyrus.h
+++ b/include/configs/cyrus.h
@@ -49,7 +49,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE2                   /* PCIE controller 2 */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */

diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h
index 37be3395738774e85fe8b8afada306044b7cd339..6796f09985112786a61ed0256707b0c62d636dc5 100644 (file)
--- a/include/configs/km/kmp204x-common.h
+++ b/include/configs/km/kmp204x-common.h
@@ -35,7 +35,6 @@
 
 #define CONFIG_SYS_FSL_CPC             /* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC             CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_PCIE1                   /* PCIE controller 1 */
 #define CONFIG_PCIE3                   /* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT            /* Use common FSL init code */

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index c8d5e89338516dce716c5c75c08b62a19876f604..f24ade96631ed60c3738b2f354b00e7d0941cf40 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -260,7 +260,6 @@
 
 #define CONFIG_MP
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */

diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h
index 041e016f52e7bae47f32cc97f4e8ebff16d99d70..c605fbe24677b58ec27df3822d6f835c64bb0fd4 100644 (file)
--- a/include/configs/p1_twr.h
+++ b/include/configs/p1_twr.h
@@ -40,7 +40,6 @@
 
 #define CONFIG_MP
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */

diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h
index 5d78560f3ee21aaffc881b34346ef5bc7338a037..2f133d2b6ed95e88790e91a9ab1ed527f784b9a1 100644 (file)
--- a/include/configs/xpedite537x.h
+++ b/include/configs/xpedite537x.h
@@ -29,7 +29,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1   /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
-#define CONFIG_FSL_ELBC                1
 
 /*
  * Multicore config

diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h
index 35e63508107ec813be6133419f31a5e74e53f5df..76e3db1706e34996f3d3a2e1c6bdc5eff9e2c364 100644 (file)
--- a/include/configs/xpedite550x.h
+++ b/include/configs/xpedite550x.h
@@ -30,7 +30,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE 1   /* indirect PCI bridge support */
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
-#define CONFIG_FSL_ELBC                1
 
 /*
  * Multicore config