remove ath_hal_reg_read_target and OS_REG_READ

and use ioread32

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>

diff --git a/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h
index bf8881183c12dee9d6d408a95b0ebdd58bf3cfe5..91d99c7a35d599147cc0f6e7fecc32af90da3e99 100755 (executable)
--- a/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h
+++ b/target_firmware/magpie_fw_dev/target/adf/adf_os_io_pvt.h
@@ -63,8 +63,6 @@ __bswap64(__uint64_t _x)
 
 #define __adf_os_reg_read16(_dev, _addr)            oops no implementation...
 
-#define __adf_os_reg_read32(_dev, _addr)            *((a_uint32_t *)(WLAN_BASE_ADDRESS + _addr))
-
 #define __adf_os_reg_read64(_dev, _addr)            oops no implementation...
 
 #define __adf_os_reg_write8(_dev, _addr, _val)      oops no implementation...

diff --git a/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h
index d4a368ffd14d6b2ec1f28b747bf4341139ce9929..56528a1eb56f6397101e23b20c8713d11e2ac69d 100755 (executable)
--- a/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h
+++ b/target_firmware/magpie_fw_dev/target/inc/adf_os_io.h
@@ -67,12 +67,16 @@
 /**
  * @brief Read a 32-bit register value
  *
- * @param[in] osdev   platform device object
  * @param[in] addr    register addr
  *
  * @return A 32-bit register value.
  */
-#define adf_os_reg_read32(osdev, addr)        __adf_os_reg_read32(osdev, addr)
+static inline a_uint32_t ioread32(a_uint32_t addr)
+{
+       return *(const volatile a_uint32_t *) addr;
+}
+
+#define ioread32_mac(addr)     ioread32(WLAN_BASE_ADDRESS + (addr))
 
 /**
  * @brief Read a 64-bit register value

diff --git a/target_firmware/wlan/ah.c b/target_firmware/wlan/ah.c
index 6f5be75939a1fb7b81f9552cb1063866dad99455..0011d320cb80bf56fc8641eeff7ea74afab88d7e 100755 (executable)
--- a/target_firmware/wlan/ah.c
+++ b/target_firmware/wlan/ah.c
@@ -179,13 +179,13 @@ ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val
 
        if (ath_hal_getcapability(ah, HAL_CAP_HT) == HAL_OK) {
                for (i = 0; i < AH_TIMEOUT_11N; i++) {
-                       if ((OS_REG_READ(ah, reg) & mask) == val)
+                       if ((ioread32_mac(reg) & mask) == val)
                                return AH_TRUE;
                        OS_DELAY(10);
                }
        } else {
                for (i = 0; i < AH_TIMEOUT_11G; i++) {
-                       if ((OS_REG_READ(ah, reg) & mask) == val)
+                       if ((ioread32_mac(reg) & mask) == val)
                                return AH_TRUE;
                        OS_DELAY(10);
                }

diff --git a/target_firmware/wlan/ah_internal.h b/target_firmware/wlan/ah_internal.h
index a43652ecd7ba70e9ae93f2ba3ea8360c1d622ac4..242ac7f4707121c58a784cb7b5ade7a7c4ff1fb9 100755 (executable)
--- a/target_firmware/wlan/ah_internal.h
+++ b/target_firmware/wlan/ah_internal.h
@@ -238,13 +238,15 @@ struct ath_hal_private {
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 #define OS_REG_RMW_FIELD(_a, _r, _f, _v)                               \
        OS_REG_WRITE(_a, _r,                                            \
-                    (OS_REG_READ(_a, _r) &~ _f) | (((_v) << _f##_S) & _f))
+                    (ioread32_mac(_r) & ~_f)           \
+                     | (((_v) << _f##_S) & _f))
 #define OS_REG_RMW(_a, _r, _set, _clr)                                 \
-        OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
+       OS_REG_WRITE(_a, _r,                                            \
+                    (ioread32_mac(_r) & ~(_clr)) | (_set))
 #define OS_REG_SET_BIT(_a, _r, _f)                     \
-       OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | _f)
+       OS_REG_WRITE(_a, _r, ioread32_mac(_r) | _f)
 #define OS_REG_CLR_BIT(_a, _r, _f)                     \
-       OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ _f)
+       OS_REG_WRITE(_a, _r, ioread32_mac(_r) & ~_f)
 
 
 /* wait for the register contents to have the specified value */

diff --git a/target_firmware/wlan/ah_osdep.c b/target_firmware/wlan/ah_osdep.c
index a039f1352d320e39ab5342d9a2b3918a3c82cd5a..92e8d6b2fc419099f6c06ee7602d2190fd453fa5 100755 (executable)
--- a/target_firmware/wlan/ah_osdep.c
+++ b/target_firmware/wlan/ah_osdep.c
@@ -88,16 +88,6 @@ ath_hal_reg_write_target(struct ath_hal *ah, a_uint32_t reg, a_uint32_t val)
        adf_os_reg_write32(ah->ah_dev, reg, val); 
 }
 
-a_uint32_t __ahdecl
-ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg)
-{
-       a_uint32_t val;
-
-       val = adf_os_reg_read32(ah->ah_dev, reg);
-
-       return val;
-}
-
 /*
  * Delay n microseconds.
  */

diff --git a/target_firmware/wlan/ah_osdep.h b/target_firmware/wlan/ah_osdep.h
index b0026dfbaae312e17633f11d53a1e98a9dbe9f40..322148f30bc53c98a91c6591a52ff131bdd0ad02 100755 (executable)
--- a/target_firmware/wlan/ah_osdep.h
+++ b/target_firmware/wlan/ah_osdep.h
@@ -147,11 +147,9 @@ extern  a_uint32_t __ahdecl ath_hal_getuptime(struct ath_hal *);
 #endif
 
 #define OS_REG_WRITE(_ah, _reg, _val)   ath_hal_reg_write_target(_ah, _reg, _val)
-#define OS_REG_READ(_ah, _reg)      ath_hal_reg_read_target(_ah, _reg)
 
 extern  void __ahdecl ath_hal_reg_write_target(struct ath_hal *ah,
         a_uint32_t reg, a_uint32_t val);
-extern  a_uint32_t __ahdecl ath_hal_reg_read_target(struct ath_hal *ah, a_uint32_t reg);
 
 #define AH_USE_EEPROM     0x00000001
 extern  struct ath_hal *_ath_hal_attach_tgt( a_uint32_t, HAL_SOFTC, adf_os_device_t,

diff --git a/target_firmware/wlan/ar5416_hw.c b/target_firmware/wlan/ar5416_hw.c
index a67ce1781e13c0e659e67fbdab3a3233f89b7e1b..5d0d1218c8508b0939afd789e7576de3e9ebcc53 100644 (file)
--- a/target_firmware/wlan/ar5416_hw.c
+++ b/target_firmware/wlan/ar5416_hw.c
@@ -129,7 +129,8 @@ ar5416Attach(HAL_SOFTC sc, adf_os_device_t dev, HAL_STATUS *status)
 
 HAL_BOOL ar5416IsInterruptPending(struct ath_hal *ah)
 {
-       a_uint32_t host_isr = OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+       a_uint32_t host_isr =
+               ioread32_mac(AR_INTR_ASYNC_CAUSE);
        /*
         * Some platforms trigger our ISR before applying power to
         * the card, so make sure.
@@ -144,8 +145,10 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
        HAL_BOOL fatal_int = AH_FALSE;
        a_uint32_t sync_cause;
 
-       if (OS_REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
-               if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
+       if (ioread32_mac(AR_INTR_ASYNC_CAUSE)
+                       & AR_INTR_MAC_IRQ) {
+               if ((ioread32_mac(AR_RTC_STATUS)
+                               & AR_RTC_STATUS_M) != AR_RTC_STATUS_ON) {
                        *masked = 0;
                        return AH_FALSE;
                }
@@ -154,7 +157,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
                return AH_FALSE;
        }
 #endif
-       isr = OS_REG_READ(ah, AR_ISR_RAC);
+       isr = ioread32_mac(AR_ISR_RAC);
        if (isr == 0xffffffff) {
                *masked = 0;
                return AH_FALSE;
@@ -174,7 +177,7 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
        if (isr & AR_ISR_BCNMISC) {
                a_uint32_t s2_s;
 
-               s2_s = OS_REG_READ(ah, AR_ISR_S2_S);
+               s2_s = ioread32_mac(AR_ISR_S2_S);
 
                if (s2_s & AR_ISR_S2_GTT) {
                        *masked |= HAL_INT_GTT;
@@ -192,8 +195,8 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
                a_uint32_t           s0_s, s1_s;
 
                *masked |= HAL_INT_TX;
-               s0_s = OS_REG_READ(ah, AR_ISR_S0_S);
-               s1_s = OS_REG_READ(ah, AR_ISR_S1_S);
+               s0_s = ioread32_mac(AR_ISR_S0_S);
+               s1_s = ioread32_mac(AR_ISR_S1_S);
                ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
                ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
                ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
@@ -201,14 +204,14 @@ HAL_BOOL ar5416GetPendingInterrupts(struct ath_hal *ah, HAL_INT *masked)
        }
 
 #ifndef AR9100
-       sync_cause = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE);
+       sync_cause = ioread32_mac(AR_INTR_SYNC_CAUSE);
        fatal_int = ((sync_cause != AR_INTR_SPURIOUS) &&
-                    (sync_cause & (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))) ?
-               AH_TRUE : AH_FALSE;
+                    (sync_cause & (AR_INTR_SYNC_HOST1_FATAL
+                     | AR_INTR_SYNC_HOST1_PERR))) ? AH_TRUE : AH_FALSE;
 
        if (AH_TRUE == fatal_int) {
                OS_REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
-               (void) OS_REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+               (void) ioread32_mac(AR_INTR_SYNC_CAUSE_CLR);
        }
 #endif
        return AH_TRUE;
@@ -223,7 +226,7 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
 
        if (omask & HAL_INT_GLOBAL) {
                OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-               (void) OS_REG_READ(ah, AR_IER);
+               (void) ioread32_mac(AR_IER);
        }
 
        mask = ints & HAL_INT_COMMON;
@@ -251,14 +254,14 @@ ar5416SetInterrupts(struct ath_hal *ah, HAL_INT ints)
        }
 
        OS_REG_WRITE(ah, AR_IMR, mask);
-       (void) OS_REG_READ(ah, AR_IMR);
+       (void) ioread32_mac(AR_IMR);
        ahp->ah_maskReg = ints;
 
        /* Re-enable interrupts if they were enabled before. */
        if (ints & HAL_INT_GLOBAL) {
                OS_REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
                /* See explanation above... */
-               (void) OS_REG_READ(ah, AR_IER);
+               (void) ioread32_mac(AR_IER);
        }
 
        OS_REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
@@ -276,8 +279,8 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah)
 {
         u_int64_t tsf;
 
-        tsf = OS_REG_READ(ah, AR_TSF_U32);
-        tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32);
+       tsf = ioread32_mac(AR_TSF_U32);
+       tsf = (tsf << 32) | ioread32_mac(AR_TSF_L32);
 
         return tsf;
 }
@@ -288,7 +291,7 @@ u_int64_t ar5416GetTsf64(struct ath_hal *ah)
 void ar5416SetRxDP(struct ath_hal *ah, a_uint32_t rxdp)
 {
        OS_REG_WRITE(ah, AR_RXDP, rxdp);
-       HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
+       HALASSERT(ioread32_mac(AR_RXDP) == rxdp);
 }
 
 HAL_BOOL ar5416StopDmaReceive(struct ath_hal *ah)
@@ -313,9 +316,13 @@ void ar5416SetRxFilter(struct ath_hal *ah, a_uint32_t bits)
                phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
        OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
        if (phybits) {
-               OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
+               OS_REG_WRITE(ah, AR_RXCFG,
+                            ioread32_mac(AR_RXCFG)
+                            | AR_RXCFG_ZLFDMA);
        } else {
-               OS_REG_WRITE(ah, AR_RXCFG,OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
+               OS_REG_WRITE(ah, AR_RXCFG,
+                            ioread32_mac(AR_RXCFG)
+                            & ~AR_RXCFG_ZLFDMA);
        }
 }
 
@@ -362,7 +369,7 @@ HAL_STATUS ar5416ProcRxDescFast_20(struct ath_hal *ah, struct ath_rx_desc *ds,
         * once and picked it up again...make sure the hw has moved on.
         */
        if ((ands->ds_rxstatus8 & AR_RxDone) == 0
-           && OS_REG_READ(ah, AR_RXDP) == pa)
+           && ioread32_mac(AR_RXDP) == pa)
                return HAL_EINPROGRESS;
 
        /*
@@ -457,7 +464,7 @@ HAL_BOOL ar5416UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
          */
         omask = ar5416SetInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
 
-        txcfg = OS_REG_READ(ah, AR_TXCFG);
+       txcfg = ioread32_mac(AR_TXCFG);
         curLevel = MS(txcfg, AR_FTRIG);
         newLevel = curLevel;
 
@@ -485,7 +492,7 @@ HAL_BOOL ar5416SetTxDP(struct ath_hal *ah, a_uint32_t q, a_uint32_t txdp)
          * Make sure that TXE is deasserted before setting the TXDP.  If TXE
          * is still asserted, setting TXDP will have no effect.
          */
-        HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
+       HALASSERT((ioread32_mac(AR_Q_TXE) & (1 << q)) == 0);
 
         OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
 
@@ -498,7 +505,7 @@ HAL_BOOL ar5416StartTxDma(struct ath_hal *ah, a_uint32_t q)
         HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
 
         /* Check to be sure we're not enabling a q that has its TXD bit set. */
-        HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
+       HALASSERT((ioread32_mac(AR_Q_TXD) & (1 << q)) == 0);
 
         OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
 
@@ -512,19 +519,21 @@ a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
         HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
         HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
 
-        npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
+       npend = ioread32_mac(AR_QSTS(q))
+               & AR_Q_STS_PEND_FR_CNT;
         if (npend == 0) {
                 /*
                  * Pending frame count (PFC) can momentarily go to zero
                  * while TXE remains asserted.  In other words a PFC of
                  * zero is not sufficient to say that the queue has stopped.
                  */
-                if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
+               if (ioread32_mac(AR_Q_TXE) & (1 << q))
                         npend = 1;
         }
 #ifdef DEBUG
         if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
-                if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
+               if (ioread32_mac(AR_Q_RDYTIMESHDN)
+                               & (1 << q)) {
                         isrPrintf("RTSD on CAB queue\n");
                         /* Clear the ReadyTime shutdown status bits */
                         OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);

diff --git a/target_firmware/wlan/if_ath.c b/target_firmware/wlan/if_ath.c
index 3cc61f7f29f094db4f2fa358e7668a0de3ba70ab..6a887126e446bdb8c9367671d50ade70105395f8 100755 (executable)
--- a/target_firmware/wlan/if_ath.c
+++ b/target_firmware/wlan/if_ath.c
@@ -1384,17 +1384,17 @@ static a_int32_t ath_reg_read_filter(struct ath_hal *ah, a_int32_t addr)
 {
        if ((addr & 0xffffe000) == 0x2000) {
                /* SEEPROM registers */
-               ath_hal_reg_read_target(ah, addr);
+               ioread32_mac(addr);
                if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0))
                        adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
 
-               return (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
+               return ioread32_mac(0x407c) & 0x0000ffff;
        } else if (addr > 0xffff)
                /* SoC registers */
                return HAL_WORD_REG_READ(addr);
        else
                /* MAC registers */
-               return ath_hal_reg_read_target(ah, addr);
+               return ioread32_mac(addr);
 }
 
 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
@@ -1427,17 +1427,17 @@ static void ath_pll_reset_ones(struct ath_hal *ah)
                HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
                /* and here to mac register */
                ath_hal_reg_write_target(ah, 0x786c,
-                        ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
+                        ioread32_mac(0x786c) | 0x6000000);
                ath_hal_reg_write_target(ah, 0x786c,
-                        ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
+                        ioread32_mac(0x786c) & (~0x6000000));
 
                HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
 
 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
                ath_hal_reg_write_target(ah, 0x7890,
-                        ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
+                        ioread32_mac(0x7890) | 0x1800000);
                ath_hal_reg_write_target(ah, 0x7890,
-                        ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
+                        ioread32_mac(0x7890) & (~0x1800000));
 #endif
                reset_pll = 1;
        }

diff --git a/target_firmware/wlan/if_owl.c b/target_firmware/wlan/if_owl.c
index b66d2767e04c0043cf46fe4ccb05793bd5caa340..3d179f43ed0b1e780913af5acef4ac7ba48ec887 100755 (executable)
--- a/target_firmware/wlan/if_owl.c
+++ b/target_firmware/wlan/if_owl.c
@@ -895,7 +895,7 @@ static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *b
        } else {
                *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
 
-               txe_val = OS_REG_READ(ah, 0x840);
+               txe_val = ioread32_mac(0x0840);
                if (!(txe_val & (1<< txq->axq_qnum)))
                        ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
        }