Remove unwanted ';' at end of define.
authorSelvamuthukumar <selva.muthukumar@e-coninfotech.com>
Wed, 8 Oct 2008 23:12:20 +0000 (18:12 -0500)
committerWolfgang Denk <wd@denx.de>
Tue, 14 Oct 2008 21:03:03 +0000 (23:03 +0200)
Currently this is not creating any problem. But it will result
in compilation error when used as below.

printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2);

Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com>
continuation of the theme based on git grep "^#define CFG_.*;$" include/

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
include/configs/EB+MCF-EV123.h
include/configs/M5272C3.h
include/configs/M5282EVB.h
include/configs/MPC8313ERDB.h
include/configs/MPC837XERDB.h
include/configs/cobra5272.h
include/configs/spc1920.h

index a949454f7ea3dbc93309c0bd81cb4d650e696abb..72f7b3fe4fba7689b85a756b9556aaec094d0c7d 100644 (file)
 #define CFG_PEHLPAR            0xC0
 #define CFG_PUAPAR             0x0F            /* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA              0x05
-#define CFG_PJPAR              0xFF;
+#define CFG_PJPAR              0xFF
 
 /*-----------------------------------------------------------------------
  * CCM configuration
index d2dcdd28a5c0a1d73b485c804044ef33557862c2..35f048e4e82bb83ad48880a016e49b5fd96fb468 100644 (file)
  * You should know what you are doing if you make changes here.
  */
 #define CFG_MBAR               0x10000000      /* Register Base Addrs */
-#define CFG_SCR                        0x0003;
-#define CFG_SPR                        0xffff;
+#define CFG_SCR                        0x0003
+#define CFG_SPR                        0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
index 5cc64c167f2c250fb69940cc246051860bf28dab..1bc877aa52dc3226bee209397422eae891289dd9 100644 (file)
 #define CFG_PEHLPAR            0xC0
 #define CFG_PUAPAR             0x0F    /* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA              0x05
-#define CFG_PJPAR              0xFF;
+#define CFG_PJPAR              0xFF
 
 #endif                         /* _CONFIG_M5282EVB_H */
index 09bb87e3b2080fa348362156b047ebd3fc656f60..30c42432284ef3b50b69b110d78a2270cb7b7669 100644 (file)
                                | SDRAM_CFG_32_BE )
                                /* 0x43080000 */
 #endif
-#define CFG_SDRAM_CFG2         0x00401000;
+#define CFG_SDRAM_CFG2         0x00401000
 /* set burst length to 8 for 32-bit data path */
 #define CFG_DDR_MODE           ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
                                | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
                                /* 0x44480632 */
-#define CFG_DDR_MODE_2         0x8000C000;
+#define CFG_DDR_MODE_2         0x8000C000
 
 #define CFG_DDR_CLK_CNTL       DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
                                /*0x02000000*/
index f818b0fdb0c46142b06435d02f36c88a0d0b05c1..4650b8d9b44a63674691f6266a3ef70f6a9a72fa 100644 (file)
 #define CFG_DDR_MODE           ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
                                | (0x0442 << SDRAM_MODE_SD_SHIFT))
                                /* 0x04400442 */ /* DDR400 */
-#define CFG_DDR_MODE2          0x00000000;
+#define CFG_DDR_MODE2          0x00000000
 
 /*
  * Memory test
index 9b729acf8edfde1cdd1bb209b2e4d45944d82cf6..ee5116e09835f92ede13a58c5eecd264e6f2d2b6 100644 (file)
@@ -262,8 +262,8 @@ from which user programs will be started */
  * ---
  */
 
-#define CFG_SCR                        0x0003;
-#define CFG_SPR                        0xffff;
+#define CFG_SCR                        0x0003
+#define CFG_SPR                        0xffff
 
 /* ---
  * Ethernet settings
index 592cef19f02f0a66f04e9c9ea910bc198dadd5a6..6594849953d4b890d4246e3b0488fe2c7623d6ac 100644 (file)
 #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
                                               BR_MS_UPMA | \
                                               BR_PS_16 | \
-                                              BR_V);
+                                              BR_V)
 
 #define CFG_MAMR (MAMR_GPL_A4DIS | \
                MAMR_RLFA_5X | \
                                        OR_SCY_4_CLK | \
                                        OR_TRLX)
 
-#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * PLD CS5
                                        OR_SCY_0_CLK | \
                                        OR_TRLX)
 
-#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * Internal Definitions