Merge branch 'master' of git://git.denx.de/u-boot-marvell
authorTom Rini <trini@ti.com>
Mon, 26 Jan 2015 00:05:40 +0000 (19:05 -0500)
committerTom Rini <trini@ti.com>
Mon, 26 Jan 2015 00:05:40 +0000 (19:05 -0500)
23 files changed:
arch/arm/cpu/armv7/ls102xa/fdt.c
arch/arm/cpu/armv7/virt-v7.c
arch/arm/include/asm/arch-ls102xa/config.h
arch/arm/include/asm/arch-ls102xa/gpio.h [new file with mode: 0644]
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/include/asm/config.h
board/freescale/ls1021aqds/MAINTAINERS
board/freescale/ls1021aqds/Makefile
board/freescale/ls1021aqds/dcu.c [new file with mode: 0644]
board/freescale/ls1021aqds/ddr.c
board/freescale/ls1021aqds/ls1021aqds.c
board/freescale/ls1021aqds/ls1021aqds_qixis.h
board/freescale/ls1021atwr/MAINTAINERS
board/freescale/ls1021atwr/ls1021atwr.c
configs/ls1021aqds_nor_lpuart_defconfig [new file with mode: 0644]
configs/ls1021atwr_nor_lpuart_defconfig [new file with mode: 0644]
drivers/crypto/fsl/Makefile
drivers/crypto/fsl/sec.c [new file with mode: 0644]
drivers/ddr/fsl/fsl_ddr_gen4.c
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h
include/fsl_ddr.h

index 989780d27348d54542a236e095f99a166e47545c..71a175392fd1c063e9149187694c0d7b8eb9f249 100644 (file)
@@ -15,6 +15,8 @@
 #include <fsl_esdhc.h>
 #endif
 #include <tsec.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <fsl_sec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -77,9 +79,24 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        int off;
        int val;
        const char *sysclk_path;
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       unsigned int svr;
+       svr = in_be32(&gur->svr);
 
        unsigned long busclk = get_bus_freq(0);
 
+       /* delete crypto node if not on an E-processor */
+       if (!IS_E_PROCESSOR(svr))
+               fdt_fixup_crypto_node(blob, 0);
+#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
+       else {
+               ccsr_sec_t __iomem *sec;
+
+               sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+               fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
+       }
+#endif
+
        fdt_fixup_ethernet(blob);
 
        off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
@@ -107,6 +124,25 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
                               "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 
+#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
+#define UBOOT_HEAD_LEN 0x1000
+       /*
+        * Reserved memory in SD boot deep sleep case.
+        * Second stage uboot binary and malloc space should be reserved.
+        * If the memory they occupied has not been reserved, then this
+        * space would be used by kernel and overwritten in uboot when
+        * deep sleep resume, which cause deep sleep failed.
+        * Since second uboot binary has a head, that space need to be
+        * reserved either(assuming its size is less than 0x1000).
+        */
+       off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
+                       CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
+                       UBOOT_HEAD_LEN);
+       if (off < 0)
+               printf("Failed to reserve memory for SD boot deep sleep: %s\n",
+                      fdt_strerror(off));
+#endif
+
 #if defined(CONFIG_FSL_ESDHC)
        fdt_fixup_esdhc(blob, bd);
 #endif
@@ -133,4 +169,17 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 
        do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
                               "clock-frequency", busclk / 2, 1);
+
+#ifdef CONFIG_QSPI_BOOT
+       off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
+                                           CONFIG_SYS_IFC_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#else
+       off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
+                                           QSPI0_BASE_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+       off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
+                                           DSPI1_BASE_ADDR);
+       fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+#endif
 }
index 651ca4015d04456df3fa172adb9924af2552c4b5..b69fd37c189c51f338ad7f1cbf766404952fc36d 100644 (file)
@@ -15,8 +15,6 @@
 #include <asm/io.h>
 #include <asm/secure.h>
 
-unsigned long gic_dist_addr;
-
 static unsigned int read_id_pfr1(void)
 {
        unsigned int reg;
@@ -68,6 +66,12 @@ static void kick_secondary_cpus_gic(unsigned long gicdaddr)
 
 void __weak smp_kick_all_cpus(void)
 {
+       unsigned long gic_dist_addr;
+
+       gic_dist_addr = get_gicd_base_address();
+       if (gic_dist_addr == -1)
+               return;
+
        kick_secondary_cpus_gic(gic_dist_addr);
 }
 
@@ -75,6 +79,7 @@ int armv7_init_nonsec(void)
 {
        unsigned int reg;
        unsigned itlinesnr, i;
+       unsigned long gic_dist_addr;
 
        /* check whether the CPU supports the security extensions */
        reg = read_id_pfr1();
index 5e934da79738a1b62ff289f81b662b0d9dba77b0..791551841c71ac81b7e203ce0da9af3992102a47 100644 (file)
 #define CONFIG_SYS_FSL_DDR_VER                 FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_SEC_COMPAT              5
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
 #else
 #error SoC not defined
 #endif
 
+#define FSL_IFC_COMPAT         "fsl,ifc"
+#define FSL_QSPI_COMPAT                "fsl,ls1-qspi"
+#define FSL_DSPI_COMPAT                "fsl,vf610-dspi"
+
 #endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
new file mode 100644 (file)
index 0000000..b704436
--- /dev/null
@@ -0,0 +1,15 @@
+/*
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+/*
+ * Dummy header file to enable CONFIG_OF_CONTROL.
+ * If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
+ * It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
+ * OF_CONTROL must have arch/gpio.h.
+ */
+
+#ifndef __ASM_ARCH_LS102XA_GPIO_H_
+#define __ASM_ARCH_LS102XA_GPIO_H_
+
+#endif
index 697d4ca4894b373d51bc7a44ad73b62402935519..f70d568d467841784e77f4b89e8c9fef77038c42 100644 (file)
@@ -105,6 +105,8 @@ struct ccsr_gur {
 
 #define SCFG_ETSECDMAMCR_LE_BD_FR      0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125      0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125      0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125      0x08000000
 #define SCFG_PIXCLKCR_PXCKEN           0x80000000
 #define SCFG_QSPI_CLKSEL               0xc0100000
 
@@ -456,6 +458,8 @@ struct ccsr_ddr {
 #define CCI400_CTRLORD_TERM_BARRIER    0x00000008
 #define CCI400_CTRLORD_EN_BARRIER      0
 #define CCI400_SHAORD_NON_SHAREABLE    0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN      0x00000002
+#define CCI400_SNOOP_REQ_EN            0x00000001
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
index 1c63f93f4d45c46c07ea14de0fab61ff141a9e50..9cc1676b6029494679b6d8c9ab5bd367bebee54f 100644 (file)
@@ -73,176 +73,6 @@ void ft_fixup_num_cores(void *blob) {
 }
 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
 
-/*
- * update crypto node properties to a specified revision of the SEC
- * called with sec_rev == 0 if not on an E processor
- */
-#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
-       static const struct sec_rev_prop {
-               u32 sec_rev;
-               u32 num_channels;
-               u32 channel_fifo_len;
-               u32 exec_units_mask;
-               u32 descriptor_types_mask;
-       } sec_rev_prop_list [] = {
-               { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
-               { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
-               { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
-               { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
-               { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
-               { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
-               { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
-       };
-       static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
-                                  sizeof("fsl,secX.Y")];
-       int crypto_node, sec_idx, err;
-       char *p;
-       u32 val;
-
-       /* locate crypto node based on lowest common compatible */
-       crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
-       if (crypto_node == -FDT_ERR_NOTFOUND)
-               return;
-
-       /* delete it if not on an E-processor */
-       if (crypto_node > 0 && !sec_rev) {
-               fdt_del_node(blob, crypto_node);
-               return;
-       }
-
-       /* else we got called for possible uprev */
-       for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
-               if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
-                       break;
-
-       if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
-               puts("warning: unknown SEC revision number\n");
-               return;
-       }
-
-       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
-       err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
-       if (err < 0)
-               printf("WARNING: could not set crypto property: %s\n",
-                      fdt_strerror(err));
-
-       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
-       err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
-       if (err < 0)
-               printf("WARNING: could not set crypto property: %s\n",
-                      fdt_strerror(err));
-
-       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
-       err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
-       if (err < 0)
-               printf("WARNING: could not set crypto property: %s\n",
-                      fdt_strerror(err));
-
-       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
-       err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
-       if (err < 0)
-               printf("WARNING: could not set crypto property: %s\n",
-                      fdt_strerror(err));
-
-       val = 0;
-       while (sec_idx >= 0) {
-               p = compat_strlist + val;
-               val += sprintf(p, "fsl,sec%d.%d",
-                       (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
-                       sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
-               sec_idx--;
-       }
-       err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
-       if (err < 0)
-               printf("WARNING: could not set crypto property: %s\n",
-                      fdt_strerror(err));
-}
-#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
-static u8 caam_get_era(void)
-{
-       static const struct {
-               u16 ip_id;
-               u8 maj_rev;
-               u8 era;
-       } caam_eras[] = {
-               {0x0A10, 1, 1},
-               {0x0A10, 2, 2},
-               {0x0A12, 1, 3},
-               {0x0A14, 1, 3},
-               {0x0A14, 2, 4},
-               {0x0A16, 1, 4},
-               {0x0A10, 3, 4},
-               {0x0A11, 1, 4},
-               {0x0A18, 1, 4},
-               {0x0A11, 2, 5},
-               {0x0A12, 2, 5},
-               {0x0A13, 1, 5},
-               {0x0A1C, 1, 5}
-       };
-
-       ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
-       u32 secvid_ms = sec_in32(&sec->secvid_ms);
-       u32 ccbvid = sec_in32(&sec->ccbvid);
-       u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
-                               SEC_SECVID_MS_IPID_SHIFT;
-       u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
-                               SEC_SECVID_MS_MAJ_REV_SHIFT;
-       u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
-
-       int i;
-
-       if (era)        /* This is '0' prior to CAAM ERA-6 */
-               return era;
-
-       for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
-               if (caam_eras[i].ip_id == ip_id &&
-                   caam_eras[i].maj_rev == maj_rev)
-                       return caam_eras[i].era;
-
-       return 0;
-}
-
-static void fdt_fixup_crypto_era(void *blob, u32 era)
-{
-       int err;
-       int crypto_node;
-
-       crypto_node = fdt_path_offset(blob, "crypto");
-       if (crypto_node < 0) {
-               printf("WARNING: Missing crypto node\n");
-               return;
-       }
-
-       err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
-                         sizeof(era));
-       if (err < 0) {
-               printf("ERROR: could not set fsl,sec-era property: %s\n",
-                      fdt_strerror(err));
-       }
-}
-
-void fdt_fixup_crypto_node(void *blob, int sec_rev)
-{
-       u8 era;
-
-       if (!sec_rev) {
-               fdt_del_node_and_alias(blob, "crypto");
-               return;
-       }
-
-       /* Add SEC ERA information in compatible */
-       era = caam_get_era();
-       if (era) {
-               fdt_fixup_crypto_era(blob, era);
-       } else {
-               printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
-                       sec_rev);
-       }
-}
-#endif
-
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
        return fdt_setprop_string(blob, offset, "phy-connection-type",
index 423a6fb8dc6419d3ef4020086777a9a3510a2011..65496d0d90a9a5c9a34e660257fca8bf6200ccae 100644 (file)
@@ -75,6 +75,7 @@
  * SEC (crypto unit) major compatible version determination
  */
 #if defined(CONFIG_MPC83xx)
+#define CONFIG_SYS_FSL_SEC_BE
 #define CONFIG_SYS_FSL_SEC_COMPAT      2
 #endif
 
index 638833dc4126fd0a8dbdfde9fbedd020bcc1b736..661526b99330ecb5093ae2b0bcd55b6d3d40ca47 100644 (file)
@@ -6,6 +6,7 @@ F:      include/configs/ls1021aqds.h
 F:     configs/ls1021aqds_nor_defconfig
 F:     configs/ls1021aqds_ddr4_nor_defconfig
 F:     configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+F:     configs/ls1021aqds_nor_lpuart_defconfig
 F:     configs/ls1021aqds_sdcard_defconfig
 F:     configs/ls1021aqds_qspi_defconfig
 F:     configs/ls1021aqds_nand_defconfig
index 3b6903c83bcd8b64bda657f041fe778d3687d4d2..ab0234412cb88b7d3c9537eea771c327190383ea 100644 (file)
@@ -7,3 +7,4 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
new file mode 100644 (file)
index 0000000..90f5bc0
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+       unsigned long long div;
+
+       div = (unsigned long long)(gd->bus_clk / 1000);
+       div *= (unsigned long long)pixclock;
+       do_div(div, 1000000000);
+
+       return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+                     const char *port,
+                     struct fb_videomode *dcu_fb_videomode)
+{
+       const char *name;
+       unsigned int pixel_format;
+       int ret;
+       u8 ch;
+
+       /* Mux I2C3+I2C4 as HSYNC+VSYNC */
+       ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+                      1, &ch, 1);
+       if (ret) {
+               printf("Error: failed to read I2C @%02x\n",
+                      CONFIG_SYS_I2C_QIXIS_ADDR);
+               return ret;
+       }
+       ch &= 0x1F;
+       ch |= 0xA0;
+       ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+                       1, &ch, 1);
+       if (ret) {
+               printf("Error: failed to write I2C @%02x\n",
+                      CONFIG_SYS_I2C_QIXIS_ADDR);
+               return ret;
+       }
+
+       if (strncmp(port, "hdmi", 4) == 0) {
+               unsigned long pixval;
+
+               name = "HDMI";
+
+               pixval = 1000000000 / dcu_fb_videomode->pixclock;
+               pixval *= 1000;
+
+               i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+               select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+               diu_set_dvi_encoder(pixval);
+               select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       } else {
+               return 0;
+       }
+
+       printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+       pixel_format = 32;
+       fsl_dcu_init(xres, yres, pixel_format);
+
+       return 0;
+}
index a539ff97913ded4a98b3e95ca0ea9cafc8f05175..6435bf9ad18f2db0da555004f3ca7808f47edf32 100644 (file)
@@ -7,6 +7,7 @@
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
+#include <asm/io.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -149,6 +150,17 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 }
 #endif
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+       void __iomem *qixis_base = (void *)QIXIS_BASE;
+
+       /* does not provide HW signals for power management */
+       clrbits_8(qixis_base + 0x21, 0x2);
+       udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
@@ -159,6 +171,11 @@ phys_size_t initdram(int board_type)
 #else
        dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+       fsl_dp_resume();
+#endif
+
        return dram_size;
 }
 
index 152da2d3e891c1641f2f75ba4c51962faf7f71f2..20eade46514114ee6432f0bedf4e10af7c99b060 100644 (file)
@@ -20,6 +20,7 @@
 #include <fsl_sec.h>
 #include <spl.h>
 
+#include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
 #ifdef CONFIG_U_QE
@@ -48,6 +49,12 @@ enum {
        MUX_TYPE_SD_PC_SG_SG,
 };
 
+enum {
+       GE0_CLK125,
+       GE2_CLK125,
+       GE1_CLK125,
+};
+
 int checkboard(void)
 {
 #ifndef CONFIG_QSPI_BOOT
@@ -177,7 +184,6 @@ int board_early_init_f(void)
 
 #ifdef CONFIG_TSEC_ENET
        out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
-       out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 #endif
 
 #ifdef CONFIG_FSL_IFC
@@ -188,6 +194,24 @@ int board_early_init_f(void)
        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
+#ifdef CONFIG_FSL_DCU_FB
+       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+       /*
+        * Enable snoop requests and DVM message requests for
+        * Slave insterface S4 (A7 core cluster)
+        */
+       out_le32(&cci->slave[4].snoop_ctrl,
+                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+       /*
+        * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+        * All transactions are treated as non-shareable
+        */
+       out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+       out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
        /* Workaround for the issue that DDR could not respond to
         * barrier transaction which is generated by executing DSB/ISB
         * instruction. Set CCI-400 control override register to
@@ -195,6 +219,11 @@ int board_early_init_f(void)
         * allow barrier transaction to DDR again */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
 
+#if defined(CONFIG_DEEP_SLEEP)
+       if (is_warm_boot())
+               fsl_dp_disable_console();
+#endif
+
        return 0;
 }
 
@@ -228,6 +257,11 @@ void board_init_f(ulong dummy)
 
        get_clocks();
 
+#if defined(CONFIG_DEEP_SLEEP)
+       if (is_warm_boot())
+               fsl_dp_disable_console();
+#endif
+
        preloader_console_init();
 
 #ifdef CONFIG_SPL_I2C_SUPPORT
@@ -241,6 +275,32 @@ void board_init_f(ulong dummy)
 }
 #endif
 
+void config_etseccm_source(int etsec_gtx_125_mux)
+{
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
+       switch (etsec_gtx_125_mux) {
+       case GE0_CLK125:
+               out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE0_CLK125);
+               debug("etseccm set to GE0_CLK125\n");
+               break;
+
+       case GE2_CLK125:
+               out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
+               debug("etseccm set to GE2_CLK125\n");
+               break;
+
+       case GE1_CLK125:
+               out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE1_CLK125);
+               debug("etseccm set to GE1_CLK125\n");
+               break;
+
+       default:
+               printf("Error! trying to set etseccm to invalid value\n");
+               break;
+       }
+}
+
 int config_board_mux(int ctrl_type)
 {
        u8 reg12, reg14;
@@ -250,6 +310,7 @@ int config_board_mux(int ctrl_type)
 
        switch (ctrl_type) {
        case MUX_TYPE_CAN:
+               config_etseccm_source(GE2_CLK125);
                reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
                break;
        case MUX_TYPE_IIC2:
@@ -259,6 +320,7 @@ int config_board_mux(int ctrl_type)
                reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
                break;
        case MUX_TYPE_SAI:
+               config_etseccm_source(GE2_CLK125);
                reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
                break;
        case MUX_TYPE_SDHC:
@@ -471,13 +533,6 @@ int board_init(void)
        /* Set CCI-400 control override register to
         * enable barrier transaction */
        out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-       /*
-        * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
-        * All transactions are treated as non-shareable
-        */
-       out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
@@ -500,6 +555,21 @@ int board_init(void)
        return 0;
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_sleep_prepare(void)
+{
+       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+
+       /* Set CCI-400 control override register to
+        * enable barrier transaction */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LS102XA_NS_ACCESS
+       enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
+#endif
+}
+#endif
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
        ft_cpu_setup(blob, bd);
index 09b3be2f9c2447a48b20a23553a9f2cba4af4f04..8e482eb0b075f07e7a197c08bb75c7549ec4bfce 100644 (file)
@@ -32,4 +32,6 @@
 
 #define QIXIS_SRDS1CLK_100             0x0
 
+#define QIXIS_DCU_BRDCFG5              0x55
+
 #endif
index 91767065faa36f0f2540d2263ea882305020fb55..e9f6f0a973a15ea6761a734b4690a0b3b028eb79 100644 (file)
@@ -5,5 +5,6 @@ F:      board/freescale/ls1021atwr/
 F:     include/configs/ls1021atwr.h
 F:     configs/ls1021atwr_nor_defconfig
 F:     configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+F:     configs/ls1021atwr_nor_lpuart_defconfig
 F:     configs/ls1021atwr_sdcard_defconfig
 F:     configs/ls1021atwr_qspi_defconfig
index 027b67e6d588a4c17ae4f86d6a018e00999670bf..bc8b00686c7c79831f6cf1ceb6b27ec04458909c 100644 (file)
@@ -263,6 +263,7 @@ int config_serdes_mux(void)
 int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
        out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -281,6 +282,20 @@ int board_early_init_f(void)
        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
+       /*
+        * Enable snoop requests and DVM message requests for
+        * Slave insterface S4 (A7 core cluster)
+        */
+       out_le32(&cci->slave[4].snoop_ctrl,
+                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+       /*
+        * Set CCI-400 Slave interface S1, S2 Shareable Override Register
+        * All transactions are treated as non-shareable
+        */
+       out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+       out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
        return 0;
 }
 
@@ -405,16 +420,6 @@ struct smmu_stream_id dev_stream_id[] = {
 
 int board_init(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
-       /*
-        * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
-        * All transactions are treated as non-shareable
-        */
-       out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        fsl_serdes_init();
 #ifndef CONFIG_QSPI_BOOT
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
new file mode 100644 (file)
index 0000000..29335ee
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021AQDS=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
new file mode 100644 (file)
index 0000000..bdab6d9
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="LPUART"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
index cb13d2e0ae65c6c80009730890448a12681e14eb..067d0a917ba6851f3d48ac7b428503d49252e994 100644 (file)
@@ -6,5 +6,6 @@
 # Version 2 as published by the Free Software Foundation.
 #
 
+obj-y += sec.o
 obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o
 obj-$(CONFIG_CMD_BLOB) += fsl_blob.o
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c
new file mode 100644 (file)
index 0000000..443ee96
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 || CONFIG_SYS_FSL_SEC_COMPAT >= 4
+#include <fsl_sec.h>
+#endif
+
+/*
+ * update crypto node properties to a specified revision of the SEC
+ * called with sec_rev == 0 if not on an E processor
+ */
+#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+       static const struct sec_rev_prop {
+               u32 sec_rev;
+               u32 num_channels;
+               u32 channel_fifo_len;
+               u32 exec_units_mask;
+               u32 descriptor_types_mask;
+       } sec_rev_prop_list[] = {
+               { 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
+               { 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
+               { 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
+               { 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
+               { 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
+               { 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
+               { 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
+       };
+       static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
+                                  sizeof("fsl,secX.Y")];
+       int crypto_node, sec_idx, err;
+       char *p;
+       u32 val;
+
+       /* locate crypto node based on lowest common compatible */
+       crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
+       if (crypto_node == -FDT_ERR_NOTFOUND)
+               return;
+
+       /* delete it if not on an E-processor */
+       if (crypto_node > 0 && !sec_rev) {
+               fdt_del_node(blob, crypto_node);
+               return;
+       }
+
+       /* else we got called for possible uprev */
+       for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
+               if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
+                       break;
+
+       if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
+               puts("warning: unknown SEC revision number\n");
+               return;
+       }
+
+       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
+       err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
+       if (err < 0)
+               printf("WARNING: could not set crypto property: %s\n",
+                      fdt_strerror(err));
+
+       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
+       err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask",
+                         &val, 4);
+       if (err < 0)
+               printf("WARNING: could not set crypto property: %s\n",
+                      fdt_strerror(err));
+
+       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
+       err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
+       if (err < 0)
+               printf("WARNING: could not set crypto property: %s\n",
+                      fdt_strerror(err));
+
+       val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
+       err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
+       if (err < 0)
+               printf("WARNING: could not set crypto property: %s\n",
+                      fdt_strerror(err));
+
+       val = 0;
+       while (sec_idx >= 0) {
+               p = compat_strlist + val;
+               val += sprintf(p, "fsl,sec%d.%d",
+                       (sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
+                       sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
+               sec_idx--;
+       }
+       err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist,
+                         val);
+       if (err < 0)
+               printf("WARNING: could not set crypto property: %s\n",
+                      fdt_strerror(err));
+}
+#elif CONFIG_SYS_FSL_SEC_COMPAT >= 4  /* SEC4 */
+static u8 caam_get_era(void)
+{
+       static const struct {
+               u16 ip_id;
+               u8 maj_rev;
+               u8 era;
+       } caam_eras[] = {
+               {0x0A10, 1, 1},
+               {0x0A10, 2, 2},
+               {0x0A12, 1, 3},
+               {0x0A14, 1, 3},
+               {0x0A14, 2, 4},
+               {0x0A16, 1, 4},
+               {0x0A10, 3, 4},
+               {0x0A11, 1, 4},
+               {0x0A18, 1, 4},
+               {0x0A11, 2, 5},
+               {0x0A12, 2, 5},
+               {0x0A13, 1, 5},
+               {0x0A1C, 1, 5}
+       };
+
+       ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+       u32 secvid_ms = sec_in32(&sec->secvid_ms);
+       u32 ccbvid = sec_in32(&sec->ccbvid);
+       u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >>
+                               SEC_SECVID_MS_IPID_SHIFT;
+       u8 maj_rev = (secvid_ms & SEC_SECVID_MS_MAJ_REV_MASK) >>
+                               SEC_SECVID_MS_MAJ_REV_SHIFT;
+       u8 era = (ccbvid & SEC_CCBVID_ERA_MASK) >> SEC_CCBVID_ERA_SHIFT;
+
+       int i;
+
+       if (era)        /* This is '0' prior to CAAM ERA-6 */
+               return era;
+
+       for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+               if (caam_eras[i].ip_id == ip_id &&
+                   caam_eras[i].maj_rev == maj_rev)
+                       return caam_eras[i].era;
+
+       return 0;
+}
+
+static void fdt_fixup_crypto_era(void *blob, u32 era)
+{
+       int err;
+       int crypto_node;
+
+       crypto_node = fdt_path_offset(blob, "crypto");
+       if (crypto_node < 0) {
+               printf("WARNING: Missing crypto node\n");
+               return;
+       }
+
+       err = fdt_setprop(blob, crypto_node, "fsl,sec-era", &era,
+                         sizeof(era));
+       if (err < 0) {
+               printf("ERROR: could not set fsl,sec-era property: %s\n",
+                      fdt_strerror(err));
+       }
+}
+
+void fdt_fixup_crypto_node(void *blob, int sec_rev)
+{
+       u8 era;
+
+       if (!sec_rev) {
+               fdt_del_node_and_alias(blob, "crypto");
+               return;
+       }
+
+       /* Add SEC ERA information in compatible */
+       era = caam_get_era();
+       if (era) {
+               fdt_fixup_crypto_era(blob, era);
+       } else {
+               printf("WARNING: Unable to get ERA for CAAM rev: %d\n",
+                      sec_rev);
+       }
+}
+#endif
index a3c01e7f1e2ffa5e977a9d8c3b77c6d033467b44..4eef0473439a98028395d7403fa8980eb21e8ed0 100644 (file)
@@ -171,6 +171,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                        ddr_out32(&ddr->debug[i], regs->debug[i]);
                }
        }
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008378
+       /* Erratum applies when accumulated ECC is used, or DBI is enabled */
+#define IS_ACC_ECC_EN(v) ((v) & 0x4)
+#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
+       if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
+           IS_DBI(regs->ddr_sdram_cfg_3))
+               ddr_setbits32(ddr->debug[28], 0x9 << 20);
+#endif
 
        /*
         * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
index 8dc04f2e574bd40eee24a31605a245b0373a4a16..2874ccc6fadd2847b98fe5018fb3c6f16479fae7 100644 (file)
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_SILENT_CONSOLE
+#endif
+
 /*
  * Size of malloc() pool
  */
@@ -72,7 +77,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SPL_PAD_TO              0x1c000
 #define CONFIG_SYS_TEXT_BASE           0x82000000
 
-#define CONFIG_SYS_SPL_MALLOC_START    0x80200000
+#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_TEXT_BASE + \
+               CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x100000
 #define CONFIG_SPL_BSS_START_ADDR      0x80100000
 #define CONFIG_SPL_BSS_MAX_SIZE                0x80000
@@ -365,11 +371,16 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Serial Port
  */
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE                        115200
 
@@ -385,6 +396,7 @@ unsigned long get_board_ddr_clk(void);
  */
 #define I2C_MUX_PCA_ADDR_PRI           0x77
 #define I2C_MUX_CH_DEFAULT             0x8
+#define I2C_MUX_CH_CH7301              0xC
 
 /*
  * MMC
@@ -426,6 +438,25 @@ unsigned long get_board_ddr_clk(void);
 #endif
 #endif
 
+/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_I2C_DVI_BUS_NUM     0
+#define CONFIG_SYS_I2C_QIXIS_ADDR      0x66
+#define CONFIG_SYS_I2C_DVI_ADDR                0x75
+#endif
+
 /*
  * eTSEC
  */
@@ -508,11 +539,19 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+       "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+       "fdt_high=0xcfffffff\0"         \
+       "initrd_high=0xcfffffff\0"      \
+       "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
        "fdt_high=0xcfffffff\0"         \
        "initrd_high=0xcfffffff\0"      \
        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
+#endif
 
 /*
  * Miscellaneous configurable options
index 66954d0a401aee4e97be648cd5566c4c6b9d6194..0a0bb5f1099ea789b8da6dabe00778745527ecf0 100644 (file)
 /*
  * Serial Port
  */
+#ifdef CONFIG_LPUART
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32B_REG
+#else
 #define CONFIG_CONS_INDEX              1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
 #define CONFIG_SYS_NS16550_CLK         get_serial_clock()
+#endif
 
 #define CONFIG_BAUDRATE                        115200
 
 
 #define CONFIG_BOOTDELAY               3
 
+#ifdef CONFIG_LPUART
+#define CONFIG_EXTRA_ENV_SETTINGS       \
+       "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
+       "initrd_high=0xcfffffff\0"      \
+       "fdt_high=0xcfffffff\0"
+#else
 #define CONFIG_EXTRA_ENV_SETTINGS      \
        "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
        "initrd_high=0xcfffffff\0"      \
        "fdt_high=0xcfffffff\0"
+#endif
 
 /*
  * Miscellaneous configurable options
index 675557ad1fd3605f07fab75477f8c61f6cd58fae..3286c95907c2419e3ccdc6cdc05a8245357459a5 100644 (file)
 #ifdef CONFIG_SYS_FSL_DDR_LE
 #define ddr_in32(a)    in_le32(a)
 #define ddr_out32(a, v)        out_le32(a, v)
+#define ddr_setbits32(a, v)    setbits_le32(a, v)
+#define ddr_clrbits32(a, v)    clrbits_le32(a, v)
+#define ddr_clrsetbits32(a, clear, set)        clrsetbits_le32(a, clear, set)
 #else
 #define ddr_in32(a)    in_be32(a)
 #define ddr_out32(a, v)        out_be32(a, v)
+#define ddr_setbits32(a, v)    setbits_be32(a, v)
+#define ddr_clrbits32(a, v)    clrbits_be32(a, v)
+#define ddr_clrsetbits32(a, clear, set)        clrsetbits_be32(a, clear, set)
 #endif
 
 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR