Add DDR_FSM_WAIT_CONTROL register address in common QC/A header

diff --git a/u-boot/include/soc/qca_soc_common.h b/u-boot/include/soc/qca_soc_common.h
index a032c6115e09a42997e21d4be003f57a6cf2bbf9..1eb0a6fe43581f9c86973fae7473a8c644f3e298 100644 (file)
--- a/u-boot/include/soc/qca_soc_common.h
+++ b/u-boot/include/soc/qca_soc_common.h
@@ -95,6 +95,7 @@
        #define QCA_AHB_MASTER_TOUT_MAX_REG                     QCA_DDR_CTRL_BASE_REG + 0x0CC
        #define QCA_AHB_MASTER_TOUT_CURR_REG            QCA_DDR_CTRL_BASE_REG + 0x0D0
        #define QCA_AHB_MASTER_TOUT_SLV_ADDR_REG        QCA_DDR_CTRL_BASE_REG + 0x0D4
+       #define QCA_DDR_FSM_WAIT_CTRL_REG                       QCA_DDR_CTRL_BASE_REG + 0x0E4
        #define QCA_DDR_CTRL_CFG_REG                            QCA_DDR_CTRL_BASE_REG + 0x108
        #define QCA_DDR_SELF_REFRESH_CTRL_REG           QCA_DDR_CTRL_BASE_REG + 0x110
        #define QCA_DDR_SELF_REFRESH_TIMER_REG          QCA_DDR_CTRL_BASE_REG + 0x114