#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
- CONFIG_ZYNQ_GEM_PHY_ADDR0);
+ CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
- CONFIG_ZYNQ_GEM_PHY_ADDR1);
+ CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
#endif
return ret;
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
+#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#if !defined(CONFIG_PHYLIB)
u32 rxbd_current;
u32 rx_first_buf;
int phyaddr;
+ u32 emio;
int init;
struct phy_device *phydev;
struct mii_dev *bus;
clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0);
break;
}
- /* FIXME maybe better to define gem address in hardware.h */
- zynq_slcr_gem_clk_setup(dev->iobase != 0xE000B000, rclk, clk);
+
+ /* Change the rclk and clk only not using EMIO interface */
+ if (!priv->emio)
+ zynq_slcr_gem_clk_setup(dev->iobase !=
+ ZYNQ_GEM_BASEADDR0, rclk, clk);
setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
ZYNQ_GEM_NWCTRL_TXEN_MASK);
return phywrite(dev, addr, reg, val);
}
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr)
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio)
{
struct eth_device *dev;
struct zynq_gem_priv *priv;
priv = dev->priv;
priv->phyaddr = phy_addr;
+ priv->emio = emio;
sprintf(dev->name, "Gem.%x", base_addr);
int txpp, int rxpp);
int xilinx_ll_temac_eth_init(bd_t *bis, unsigned long base_addr, int flags,
unsigned long ctrl_addr);
-int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr);
+int zynq_gem_initialize(bd_t *bis, int base_addr, int phy_addr, u32 emio);
/*
* As long as the Xilinx xps_ll_temac ethernet driver has not its own interface
* exported by a public hader file, we need a global definition at this point.