ram: rk3399: Introduce sys_reg3 for more capacity info

cs0_row, cs1_row and cs1_col needs more bits to show its
correct value, update to make use of both sys_reg2,
sys_reg3.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
(Squash similar patches into one patch)
Signed-off-by: Kever Yang <Kever.yang@rock-chips.com>

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 4749233226624bb72f5caf08c0ae688000faf46a..f5c99fea8b378835f04d0187a2232fc502c9b32f 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -90,12 +90,8 @@ struct sdram_base_params {
                                        SYS_REG_BK_SHIFT(ch))
 #define SYS_REG_CS0_ROW_SHIFT(ch)      (6 + (ch) * 16)
 #define SYS_REG_CS0_ROW_MASK           3
-#define SYS_REG_ENC_CS0_ROW(n, ch)     (((n) - 13) << \
-                                       SYS_REG_CS0_ROW_SHIFT(ch))
 #define SYS_REG_CS1_ROW_SHIFT(ch)      (4 + (ch) * 16)
 #define SYS_REG_CS1_ROW_MASK           3
-#define SYS_REG_ENC_CS1_ROW(n, ch)     (((n) - 13) << \
-                                       SYS_REG_CS1_ROW_SHIFT(ch))
 #define SYS_REG_BW_SHIFT(ch)           (2 + (ch) * 16)
 #define SYS_REG_BW_MASK                        3
 #define SYS_REG_ENC_BW(n, ch)          ((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
@@ -103,6 +99,23 @@ struct sdram_base_params {
 #define SYS_REG_DBW_MASK               3
 #define SYS_REG_ENC_DBW(n, ch)         ((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+                       (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+                       (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+                                    (5 + 2 * (ch)); \
+               } while (0)
+
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+                       (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+                       (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+                       (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+                       (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+                                    (4 + 2 * (ch)); \
+               } while (0)
+
+#define SYS_REG_CS1_COL_SHIFT(ch)      (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
 

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 38ae6d174a150911b8d43b1587ed5e2b611af54f..fed9f94840846bbc772626d8e8e513c2f1c7f1f6 100644 (file)
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram,
                            const struct rk3399_sdram_params *params)
 {
        u32 sys_reg2 = 0;
+       u32 sys_reg3 = 0;
        unsigned int channel, idx;
 
        sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
@@ -1094,10 +1095,13 @@ static void dram_all_config(struct dram_info *dram,
                sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
                sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
                sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-               sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
-               sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
                sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
                sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+               SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+               if (info->cap_info.cs1_row)
+                       SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
+                                           sys_reg3, channel);
+               sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
 
                ddr_msch_regs = dram->chan[channel].msch;
                noc_timing = &params->ch[channel].noc_timings;
@@ -1119,6 +1123,7 @@ static void dram_all_config(struct dram_info *dram,
        }
 
        writel(sys_reg2, &dram->pmugrf->os_reg2);
+       writel(sys_reg3, &dram->pmugrf->os_reg3);
        rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
                     params->base.stride << 10);