arm: dts: socfpga: stratix10: update dtsi and dts
authorLey Foon Tan <ley.foon.tan@intel.com>
Fri, 18 May 2018 14:05:35 +0000 (22:05 +0800)
committerMarek Vasut <marex@denx.de>
Fri, 18 May 2018 08:30:48 +0000 (10:30 +0200)
Update dtsi and dts files for resets, phy node and other properties.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/dts/socfpga_stratix10.dtsi
arch/arm/dts/socfpga_stratix10_socdk.dts

index db8eb7ce7a80e5289a010e7186884593103d44b6..ccd3f32301e6beb8ee37769d731c24c41ffff8b2 100644 (file)
@@ -80,6 +80,7 @@
                device_type = "soc";
                interrupt-parent = <&intc>;
                ranges = <0 0 0 0xffffffff>;
+               u-boot,dm-pre-reloc;
 
                clkmgr@ffd1000 {
                        compatible = "altr,clk-mgr";
@@ -92,7 +93,7 @@
                        interrupts = <0 90 4>;
                        interrupt-names = "macirq";
                        mac-address = [00 00 00 00 00 00];
-                       resets = <&rst EMAC0_RESET>;
+                       resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
                        reset-names = "stmmaceth";
                        status = "disabled";
                };
                        interrupts = <0 91 4>;
                        interrupt-names = "macirq";
                        mac-address = [00 00 00 00 00 00];
-                       resets = <&rst EMAC1_RESET>;
+                       resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
                        reset-names = "stmmaceth";
                        status = "disabled";
                };
                        interrupts = <0 92 4>;
                        interrupt-names = "macirq";
                        mac-address = [00 00 00 00 00 00];
-                       resets = <&rst EMAC2_RESET>;
+                       resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
                        reset-names = "stmmaceth";
                        status = "disabled";
                };
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <0 110 4>;
+                               bank-name = "porta";
                        };
                };
 
                                interrupt-controller;
                                #interrupt-cells = <2>;
                                interrupts = <0 111 4>;
+                               bank-name = "portb";
                        };
                };
 
                        reg = <0xffc02800 0x100>;
                        interrupts = <0 103 4>;
                        resets = <&rst I2C0_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
                        reg = <0xffc02900 0x100>;
                        interrupts = <0 104 4>;
                        resets = <&rst I2C1_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
                        reg = <0xffc02a00 0x100>;
                        interrupts = <0 105 4>;
                        resets = <&rst I2C2_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
                        reg = <0xffc02b00 0x100>;
                        interrupts = <0 106 4>;
                        resets = <&rst I2C3_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
                        reg = <0xffc02c00 0x100>;
                        interrupts = <0 107 4>;
                        resets = <&rst I2C4_RESET>;
+                       reset-names = "i2c";
                        status = "disabled";
                };
 
                        reg = <0xff808000 0x1000>;
                        interrupts = <0 96 4>;
                        fifo-depth = <0x400>;
-                       resets = <&rst SDMMC_RESET>;
-                       reset-names = "reset";
+                       resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+                       u-boot,dm-pre-reloc;
                        status = "disabled";
                };
 
                        compatible = "altr,rst-mgr";
                        reg = <0xffd11000 0x1000>;
                        altr,modrst-offset = <0x20>;
+                       u-boot,dm-pre-reloc;
                };
 
                spi0: spi@ffda4000 {
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        resets = <&rst UART0_RESET>;
+                       clock-frequency = <100000000>;
+                       u-boot,dm-pre-reloc;
                        status = "disabled";
                };
 
                        reg = <0xffd00200 0x100>;
                        interrupts = <0 117 4>;
                        resets = <&rst WATCHDOG0_RESET>;
+                       u-boot,dm-pre-reloc;
                        status = "disabled";
                };
 
index d5f43a23e7e5fcdb542408eab3ede4003cc646c4..c6ab0ae9923ad5c4ef2adc09e70de1bd088802b4 100644 (file)
 &mmc {
        status = "okay";
        cap-sd-highspeed;
+       cap-mmc-highspeed;
        broken-cd;
        bus-width = <4>;
+       drvsel = <3>;
+       smplsel = <0>;
 };
 
 &uart0 {