mdelay(1000);
}
-void dprint_buffer(unsigned char *buf, int len)
-{
- int i, j;
-
- i = 0;
- j = 0;
- printf("\n\r");
-
- for (i = 0; i < len; i++) {
- printf("%02x ", *buf++);
- j++;
- if (j == 16) {
- printf("\n\r");
- j = 0;
- }
- }
- printf("\n\r");
-}
-
static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
{
printf("Status FIS dump:\n\r");
printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
}
-static int ata_wait_register(volatile unsigned *addr, u32 mask,
+static int ata_wait_register(unsigned __iomem *addr, u32 mask,
u32 val, u32 timeout_msec)
{
int i;
cmd_hdr_tbl_t *cmd_hdr;
u32 cda;
u32 val32;
- fsl_sata_reg_t *reg;
+ fsl_sata_reg_t __iomem *reg;
u32 sig;
int i;
fsl_sata_t *sata;
return 0;
}
-/* Hardware reset, like Power-on and COMRESET */
-void fsl_sata_hardware_reset(u32 reg_base)
-{
- fsl_sata_reg_t *reg = (fsl_sata_reg_t *)reg_base;
- u32 scontrol;
-
- /* Disable the SATA interface and put PHY offline */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x304;
- out_le32(®->scontrol, scontrol);
-
- /* No speed strict */
- scontrol = in_le32(®->scontrol);
- scontrol = scontrol & ~0x0f0;
- out_le32(®->scontrol, scontrol);
-
- /* Issue PHY wake/reset, Hardware_reset_asserted */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x301;
- out_le32(®->scontrol, scontrol);
-
- mdelay(100);
-
- /* Resume PHY, COMRESET negated, the device initialize hardware
- * and execute diagnostics, send good status-signature to host,
- * which is D2H register FIS, and then the device enter idle state.
- */
- scontrol = in_le32(®->scontrol);
- scontrol = (scontrol & 0x0f0) | 0x300;
- out_le32(®->scontrol, scontrol);
-
- mdelay(100);
- return;
-}
-
-static void fsl_sata_dump_regs(fsl_sata_reg_t *reg)
+static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
{
printf("\n\rSATA: %08x\n\r", (u32)reg);
printf("CQR: %08x\n\r", in_le32(®->cqr));
u32 prde_count;
u32 val32;
u32 ttl;
- fsl_sata_reg_t *reg = sata->reg_base;
+ fsl_sata_reg_t __iomem *reg = sata->reg_base;
int i;
/* Check xfer length */
return blkcnt;
}
-void fsl_sata_flush_cache(int dev)
+static void fsl_sata_flush_cache(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
return blkcnt;
}
-u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
+static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
+ int is_write)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
return blkcnt;
}
-void fsl_sata_flush_cache_ext(int dev)
+static void fsl_sata_flush_cache_ext(int dev)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
struct sata_fis_h2d h2d, *cfis = &h2d;
fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
}
-/* Software reset, set SRST of the Device Control register */
-void fsl_sata_software_reset(int dev)
-{
- return;
-}
-
static void fsl_sata_init_wcache(int dev, u16 *id)
{
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return sata->flush_ext;
}
-u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
const void *buffer, int is_write)
{
u32 start, blks;
return blkcnt;
}
-u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer,
- int is_write)
+static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
* Command Header Entry
*/
typedef struct cmd_hdr_entry {
- u32 cda; /* Command Descriptor Address, 4 bytes aligned */
- u32 prde_fis_len; /* Number of PRD entries and FIS length */
- u32 ttl; /* Total transfer length */
- u32 attribute; /* the attribute of command */
+ __le32 cda; /* Command Descriptor Address,
+ 4 bytes aligned */
+ __le32 prde_fis_len; /* Number of PRD entries and FIS length */
+ __le32 ttl; /* Total transfer length */
+ __le32 attribute; /* the attribute of command */
} __attribute__ ((packed)) cmd_hdr_entry_t;
#define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
* PRD entry - Physical Region Descriptor entry
*/
typedef struct prd_entry {
- u32 dba; /* Data base address, 4 bytes aligned */
+ __le32 dba; /* Data base address, 4 bytes aligned */
u32 res1;
u32 res2;
- u32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
+ __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
} __attribute__ ((packed)) prd_entry_t;
#define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry)
#include <fis.h>
#include <sata.h>
#include <libata.h>
+#include <sata.h>
#include "sata_sil.h"
/* Convert sectorsize to wordsize */
return blkcnt;
}
-ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
return blkcnt;
}
-ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
- const void *buffer, int is_write)
+static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
return blkcnt;
}
-void sil_sata_cmd_flush_cache(int dev)
+static void sil_sata_cmd_flush_cache(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;
sil_exec_cmd(dev, pcmd, 0);
}
-void sil_sata_cmd_flush_cache_ext(int dev)
+static void sil_sata_cmd_flush_cache_ext(int dev)
{
struct sil_cmd_block cmdb, *pcmd = &cmdb;