Minor Coding Style Cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>

diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README
index 022c023ae245ae13fbc52ae3f1b54f2bf1106c60..7f18aaa1b2a1aff66b20f5e20c8acd57c016a814 100644 (file)
--- a/board/freescale/p1010rdb/README
+++ b/board/freescale/p1010rdb/README
@@ -146,7 +146,6 @@ Build and burn u-boot to NAND flash
 3. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
 
 
-
 Build and burn u-boot to SPI flash
 ==================================
 1. Build u-boot-spi.bin image
@@ -166,7 +165,6 @@ Build and burn u-boot to SPI flash
 3. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
 
 
-
 CPLD POR setting registers
 ==========================
 1. Set POR switch selection register (addr 0xFFB00011) to 0.
@@ -197,7 +195,6 @@ Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
        => reset
 
 
-
 Boot Linux from network using TFTP on P1010RDB
 ==============================================
 Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.

diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx
index 2753b45b0b69d57fbcf75083840629502c317ed9..5a4b591a89a2795993d94627a3ca43038c2b14ab 100644 (file)
--- a/doc/README.mpc85xx
+++ b/doc/README.mpc85xx
@@ -26,15 +26,15 @@ Major Config Switches during various boot Modes
 ----------------------------------------------
 
 NOR boot
-                !defined(CONFIG_SYS_RAMBOOT)
+               !defined(CONFIG_SYS_RAMBOOT)
 NOR boot Secure
-                !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+               !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 RAMBOOT(SD, SPI & NAND boot)
-                 defined(CONFIG_SYS_RAMBOOT)
+                defined(CONFIG_SYS_RAMBOOT)
 RAMBOOT Secure (SD, SPI & NAND)
-                 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+                defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 NAND SPL BOOT
-                 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
+                defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
 
 
 TLB Entries during u-boot execution
@@ -45,44 +45,44 @@ Note: Sequence number is in order of execution
 A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
 
    1) TLB entry to overcome e500 v1/v2 debug restriction
-       Location   : Label "_start_e500"
+       Location          : Label "_start_e500"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
        Properties : 256K, AS0, I, IPROT
 
    2) TLB entry for working in AS1
-       Location   : Label "create_init_ram_area"
+       Location          : Label "create_init_ram_area"
        TLB Entry  : 15
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
        Properties : 1M, AS1, I, G, IPROT
 
    3) TLB entry for the stack during AS1
-       Location   : Lable "create_init_ram_area"
+       Location          : Lable "create_init_ram_area"
        TLB Entry  : 14
        EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
-       Location   : cpu_init_early_f
+       Location          : cpu_init_early_f
        TLB Entry  : 13
        EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) Invalidate unproctected TLB Entries
-       Location   : cpu_init_early_f
+       Location          : cpu_init_early_f
        Invalidated: 13
 
    6) Create TLB entries as per boards/freescale/<board>/tlb.c
-       Location   : cpu_init_early_f --> init_tlbs()
+       Location          : cpu_init_early_f --> init_tlbs()
        Properties : ..., AS0, ...
       Please note It can overwrites previous TLB Entries.
 
    7) Disable TLB Entries of AS1
-       Location   : cpu_init_f --> disable_tlb()
-       Disable    : 15, 14
+       Location          : cpu_init_f --> disable_tlb()
+       Disable   : 15, 14
 
    8) Update Flash's TLB entry
-       Location   : Board_init_r
+       Location          : Board_init_r
        TLB entry  : Search from TLB entries
        EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT
@@ -91,7 +91,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
 B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 
    1) TLB entry to overcome e500 v1/v2 debug restriction
-       Location   : Label "_start_e500"
+       Location          : Label "_start_e500"
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
 #if defined(CONFIG_SECURE_BOOT)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
@@ -102,7 +102,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 #endif
 
    2) TLB entry for working in AS1
-       Location   : Label "create_init_ram_area"
+       Location          : Label "create_init_ram_area"
        TLB Entry  : 15
 #if defined(CONFIG_SECURE_BOOT)
        EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
@@ -113,54 +113,54 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
 #endif
 
    3) TLB entry for the stack during AS1
-       Location   : Lable "create_init_ram_area"
+       Location          : Lable "create_init_ram_area"
        TLB Entry  : 14
        EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
        Properties : 16K, AS1, IPROT
 
    4) TLB entry for CCSRBAR during AS1 execution
-       Location   : cpu_init_early_f
+       Location          : cpu_init_early_f
        TLB Entry  : 13
        EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
        Properties : 1M, AS1, I, G
 
    5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
-       Location   : cpu_init_early_f
+       Location          : cpu_init_early_f
        TLB Entry  : 9
        EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
        Properties : 1M, AS1, I
 
    6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
-       Location   : cpu_init_early_f --> setup_ifc
+       Location          : cpu_init_early_f --> setup_ifc
        TLB Entry  : Get Flash TLB
        EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
        Properties : 4M, AS1, I, G, IPROT
 
    7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
-       Location   : cpu_init_early_f --> setup_ifc
+       Location          : cpu_init_early_f --> setup_ifc
        TLB Entry  : CONFIG_SYS_PPC_E500_DEBUG_TLB
        EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
        Properties : 4M, AS0, I, G, IPROT
 
    8) Invalidate unproctected TLB Entries
-       Location   : cpu_init_early_f
+       Location          : cpu_init_early_f
        Invalidated: 13, 9
 
    9) Create TLB entries as per boards/freescale/<board>/tlb.c
-       Location   : cpu_init_early_f --> init_tlbs()
+       Location          : cpu_init_early_f --> init_tlbs()
        Properties : ..., AS0, ...
       Note: It can overwrites previous TLB Entries
 
    10) Disable TLB Entries of AS1
-       Location   : cpu_init_f --> disable_tlb()
-       Disable    : 15, 14
+       Location          : cpu_init_f --> disable_tlb()
+       Disable   : 15, 14
 
    11) Create DDR's TLB entriy
-       Location   : Board_init_f -> init_func_ram -> initdram
+       Location          : Board_init_f -> init_func_ram -> initdram
        TLB entry  : Search free TLB entry
 
    12) Update Flash's TLB entry
-       Location   : Board_init_r
+       Location          : Board_init_r
        TLB entry  : Search from TLB entries
        EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
        Properties : Board specific size, AS0, I, G, IPROT