+--- a/arch/mips/bcm63xx/dev-hsspi.c
++++ b/arch/mips/bcm63xx/dev-hsspi.c
+@@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
+
+ int __init bcm63xx_hsspi_register(void)
+ {
+- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
+ return -ENODEV;
+
+ spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
+--- a/arch/mips/bcm63xx/dev-enet.c
++++ b/arch/mips/bcm63xx/dev-enet.c
+@@ -176,7 +176,8 @@ static int __init register_shared(void)
+ else
+ shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
+
+- if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
++ if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
++ BCMCPU_IS_63268())
+ chan_count = 32;
+ else if (BCMCPU_IS_6345())
+ chan_count = 8;
+@@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm
+ {
+ int ret;
+
+- if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
++ if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
++ !BCMCPU_IS_63268())
+ return -ENODEV;
+
+ ret = register_shared();
+@@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm
+ enetsw_pd.num_ports = ENETSW_PORTS_6328;
+ else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
+ enetsw_pd.num_ports = ENETSW_PORTS_6368;
++ else if (BCMCPU_IS_63268())
++ enetsw_pd.num_ports = ENETSW_PORTS_63268;
+
+ enetsw_pd.dma_has_sram = true;
+ enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
+--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
++++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
+@@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data {
+ #define ENETSW_MAX_PORT 8
+ #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
+ #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
++#define ENETSW_PORTS_63268 4 /* 3 FE PHY + 1 RGMII */
+
+ #define ENETSW_RGMII_PORT0 4
+