+
+#ifdef CONFIG_CAN_DRIVER
+ /*
+ * According to timing specifications EAD must be
+ * set if Local Bus Clock is > 83 MHz.
+ */
+ if (lbc_hz > 83)
+ out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
+ else
+ out_be32 (&lbc->or2, CFG_OR2_CAN);
+ out_be32 (&lbc->br2, CFG_BR2_CAN);
+
+ /* LGPL4 is UPWAIT */
+ out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
+
+ /* Initialize UPMC for CAN: single read */
+ upmc_write (0x00, 0xFFFFED00);
+ upmc_write (0x01, 0xCCFFCC00);
+ upmc_write (0x02, 0x00FFCF00);
+ upmc_write (0x03, 0x00FFCF00);
+ upmc_write (0x04, 0x00FFDC00);
+ upmc_write (0x05, 0x00FFCF00);
+ upmc_write (0x06, 0x00FFED00);
+ upmc_write (0x07, 0x3FFFCC07);
+
+ /* Initialize UPMC for CAN: single write */
+ upmc_write (0x18, 0xFFFFED00);
+ upmc_write (0x19, 0xCCFFEC00);
+ upmc_write (0x1A, 0x00FFED80);
+ upmc_write (0x1B, 0x00FFED80);
+ upmc_write (0x1C, 0x00FFFC00);
+ upmc_write (0x1D, 0x0FFFEC00);
+ upmc_write (0x1E, 0x0FFFEF00);
+ upmc_write (0x1F, 0x3FFFEC05);
+#endif /* CONFIG_CAN_DRIVER */