+#ifdef CONFIG_DM_I2C
+
+int ihs_i2c_probe(struct udevice *bus)
+{
+ struct ihs_i2c_priv *priv = dev_get_priv(bus);
+ int addr;
+
+ addr = dev_read_u32_default(bus, "reg", -1);
+
+ priv->addr = addr;
+
+ return 0;
+}
+
+static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
+{
+ struct ihs_i2c_priv *priv = dev_get_priv(bus);
+
+ if (speed != priv->speed && priv->speed != 0)
+ return 1;
+
+ priv->speed = speed;
+
+ return 0;
+}
+
+static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+ struct i2c_msg *dmsg, *omsg, dummy;
+
+ memset(&dummy, 0, sizeof(struct i2c_msg));
+
+ /* We expect either two messages (one with an offset and one with the
+ * actucal data) or one message (just data)
+ */
+ if (nmsgs > 2 || nmsgs == 0) {
+ debug("%s: Only one or two messages are supported.", __func__);
+ return -1;
+ }
+
+ omsg = nmsgs == 1 ? &dummy : msg;
+ dmsg = nmsgs == 1 ? msg : msg + 1;
+
+ if (dmsg->flags & I2C_M_RD)
+ return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
+ omsg->len, dmsg->buf, dmsg->len,
+ I2COP_READ);
+ else
+ return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
+ omsg->len, dmsg->buf, dmsg->len,
+ I2COP_WRITE);
+}
+
+static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
+ u32 chip_flags)
+{
+ uchar buffer[2];
+
+ if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
+ return 1;
+
+ return 0;
+}
+
+static const struct dm_i2c_ops ihs_i2c_ops = {
+ .xfer = ihs_i2c_xfer,
+ .probe_chip = ihs_i2c_probe_chip,
+ .set_bus_speed = ihs_i2c_set_bus_speed,
+};
+
+static const struct udevice_id ihs_i2c_ids[] = {
+ { .compatible = "gdsys,ihs_i2cmaster", },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(i2c_ihs) = {
+ .name = "i2c_ihs",
+ .id = UCLASS_I2C,
+ .of_match = ihs_i2c_ids,
+ .probe = ihs_i2c_probe,
+ .priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
+ .ops = &ihs_i2c_ops,
+};
+
+#else /* CONFIG_DM_I2C */
+