The driver limits the config space base to 32bit, however it can be
64bit on 64bit iMX hardware too. Remove that limitation. This patch
has no impact on the iMX6, which is the only SoC currently supported
by this driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
/* Region #0 is used for Outbound CFG space access. */
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
/* Region #0 is used for Outbound CFG space access. */
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
- writel((u32)priv->cfg_base, priv->dbi_base + PCIE_ATU_LOWER_BASE);
- writel(0, priv->dbi_base + PCIE_ATU_UPPER_BASE);
- writel((u32)priv->cfg_base + MX6_ROOT_SIZE,
+ writel(lower_32_bits((uintptr_t)priv->cfg_base),
+ priv->dbi_base + PCIE_ATU_LOWER_BASE);
+ writel(upper_32_bits((uintptr_t)priv->cfg_base),
+ priv->dbi_base + PCIE_ATU_UPPER_BASE);
+ writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE),
priv->dbi_base + PCIE_ATU_LIMIT);
writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
priv->dbi_base + PCIE_ATU_LIMIT);
writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
/*
* PCI Express accessors
*/
/*
* PCI Express accessors
*/
-static uint32_t get_bus_address(pci_dev_t d, int where)
+static void __iomem *get_bus_address(pci_dev_t d, int where)
+ void __iomem *va_address;
/* Reconfigure Region #0 */
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
/* Reconfigure Region #0 */
writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT);
writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
if (PCI_BUS(d) == 0) {
writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1);
if (PCI_BUS(d) == 0) {
- va_address = (u32)priv->dbi_base;
+ va_address = priv->dbi_base;
} else {
writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
} else {
writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET);
- va_address = (u32)priv->cfg_base;
+ va_address = priv->cfg_base;
}
va_address += (where & ~0x3);
}
va_address += (where & ~0x3);
static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 *val)
{
static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 *val)
{
+ void __iomem *va_address;
int ret;
ret = imx_pcie_addr_valid(d);
int ret;
ret = imx_pcie_addr_valid(d);
static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 val)
{
static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
int where, u32 val)
{
- uint32_t va_address = 0;
+ void __iomem *va_address = NULL;
int ret;
ret = imx_pcie_addr_valid(d);
int ret;
ret = imx_pcie_addr_valid(d);