-#ifndef CONFIG_SPL_BUILD
-static void fixup_enet_clock(void)
-{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct gpio_desc nint;
- struct gpio_desc reset;
- int ret;
-
- /* Set Ref Clock to 50 MHz */
- enable_fec_anatop_clock(0, ENET_50MHZ);
-
- /* Set GPIO_16 as ENET_REF_CLK_OUT */
- setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-
- /* Request GPIO Pins to reset Ethernet with new clock */
- ret = dm_gpio_lookup_name("GPIO4_7", &nint);
- if (ret) {
- printf("Unable to lookup GPIO4_7\n");
- return;
- }
-
- ret = dm_gpio_request(&nint, "eth0_nInt");
- if (ret) {
- printf("Unable to request eth0_nInt\n");
- return;
- }
-
- /* Ensure nINT is input or PHY won't startup */
- dm_gpio_set_dir_flags(&nint, GPIOD_IS_IN);
-
- ret = dm_gpio_lookup_name("GPIO4_9", &reset);
- if (ret) {
- printf("Unable to lookup GPIO4_9\n");
- return;
- }
-
- ret = dm_gpio_request(&reset, "eth0_reset");
- if (ret) {
- printf("Unable to request eth0_reset\n");
- return;
- }
-
- /* Reset LAN8710A PHY */
- dm_gpio_set_dir_flags(&reset, GPIOD_IS_OUT);
- dm_gpio_set_value(&reset, 0);
- udelay(150);
- dm_gpio_set_value(&reset, 1);
- mdelay(50);
-}
-#endif
-