The get_pll() function can do the wrong thing if passed values that are
out of range. Add checks for this and add a function which can return
a 'simple' PLL. This can be defined by SoCs with their own clocks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id);
/* Returns a pointer to the clock source register for a peripheral */
u32 *get_periph_source_reg(enum periph_id periph_id);
+/* Returns a pointer to the given 'simple' PLL */
+struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
+
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
assert(clock_id_is_pll(clkid));
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
assert(clock_id_is_pll(clkid));
+ if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
+ debug("%s: Invalid PLL\n", __func__);
+ return NULL;
+ }
return &clkrst->crc_pll[clkid];
}
return &clkrst->crc_pll[clkid];
}
+__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
+{
+ return NULL;
+}
+
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
u32 *divp, u32 *cpcon, u32 *lfcon)
{
int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
u32 *divp, u32 *cpcon, u32 *lfcon)
{
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_pll *pll = get_pll(clkid);
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_pll *pll = get_pll(clkid);
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
*/
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
*/
- data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
- writel(data, &pll->pll_misc);
+ misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
data |= divp << PLLU_VCO_FREQ_SHIFT;
else
data |= divp << PLL_DIVP_SHIFT;
data |= divp << PLLU_VCO_FREQ_SHIFT;
else
data |= divp << PLL_DIVP_SHIFT;
- writel(data, &pll->pll_base);
+ if (pll) {
+ writel(misc_data, &pll->pll_misc);
+ writel(data, &pll->pll_base);
+ } else {
+ struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
+
+ if (!pll) {
+ debug("%s: Uknown simple PLL %d\n", __func__, clkid);
+ return 0;
+ }
+ writel(misc_data, &pll->pll_misc);
+ writel(data, &pll->pll_base);
+ }
/* calculate the stable time */
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
/* calculate the stable time */
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
return parent_rate;
pll = get_pll(clkid);
return parent_rate;
pll = get_pll(clkid);
base = readl(&pll->pll_base);
/* Oh for bf_unpack()... */
base = readl(&pll->pll_base);
/* Oh for bf_unpack()... */