The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card interface. Use the same differentiation and allow
the platform to constrain the peripheral interface.
Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
13 files changed:
free(host);
return -ENODEV;
}
free(host);
return -ENODEV;
}
+ host->max_clk = max_clk;
- add_sdhci(host, max_clk, min_clk);
+ add_sdhci(host, 0, min_clk);
if (!max_clk)
return -EINVAL;
if (!max_clk)
return -EINVAL;
- ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ);
+ host->max_clk = max_clk;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
host->ioaddr = (void *)(unsigned long)regbase;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
host->ioaddr = (void *)(unsigned long)regbase;
host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT;
+ host->max_clk = emmc_freq;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &bcm2835_ops;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &bcm2835_ops;
- add_sdhci(host, emmc_freq, MIN_FREQ);
+ add_sdhci(host, 0, MIN_FREQ);
host->name = "FTSDC021";
host->ioaddr = (void __iomem *)regbase;
host->quirks = 0;
host->name = "FTSDC021";
host->ioaddr = (void __iomem *)regbase;
host->quirks = 0;
- add_sdhci(host, freq, 0);
+ host->max_clk = freq;
+ add_sdhci(host, 0, 0);
host->name = "kona-sdhci";
host->ioaddr = reg_base;
host->quirks = quirks;
host->name = "kona-sdhci";
host->ioaddr = reg_base;
host->quirks = quirks;
+ host->max_clk = max_clk;
if (init_kona_mmc_core(host)) {
free(host);
return -EINVAL;
}
if (init_kona_mmc_core(host)) {
free(host);
return -EINVAL;
}
- add_sdhci(host, max_clk, min_clk);
+ add_sdhci(host, 0, min_clk);
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
/* Init clocks */
ret = msm_sdc_clk_init(dev);
if (ret)
/* Init clocks */
ret = msm_sdc_clk_init(dev);
if (ret)
host->name = MVSDH_NAME;
host->ioaddr = (void *)regbase;
host->quirks = quirks;
host->name = MVSDH_NAME;
host->ioaddr = (void *)regbase;
host->quirks = quirks;
+ host->max_clk = max_clk;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
memset(&mv_ops, 0, sizeof(struct sdhci_ops));
mv_ops.write_b = mv_sdhci_writeb;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
memset(&mv_ops, 0, sizeof(struct sdhci_ops));
mv_ops.write_b = mv_sdhci_writeb;
sdhci_mvebu_mbus_config((void __iomem *)regbase);
}
sdhci_mvebu_mbus_config((void __iomem *)regbase);
}
- return add_sdhci(host, max_clk, min_clk);
+ return add_sdhci(host, 0, min_clk);
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)(ulong)iobase;
mmc_host->quirks = 0;
dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
mmc_host->ioaddr = (void *)(ulong)iobase;
mmc_host->quirks = 0;
ret = add_sdhci(mmc_host, 0, 0);
if (ret)
return ret;
ret = add_sdhci(mmc_host, 0, 0);
if (ret)
return ret;
- ret = add_sdhci(host, f_min_max[1], f_min_max[0]);
+ host->max_clk = f_min_max[1];
+
+ ret = add_sdhci(host, 0, f_min_max[0]);
if (ret)
return ret;
host->mmc->dev = dev;
if (ret)
return ret;
host->mmc->dev = dev;
}
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
}
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
+ host->max_clk = max_frequency;
- ret = sdhci_setup_cfg(&plat->cfg, host, max_frequency,
- EMMC_MIN_FREQ);
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
host->mmc = &plat->mmc;
if (ret)
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
SDHCI_QUIRK_32BIT_DMA_ADDR |
SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
+ host->max_clk = 52000000;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &s5p_sdhci_ops;
host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
host->ops = &s5p_sdhci_ops;
host->host_caps |= MMC_MODE_8BIT;
#ifndef CONFIG_BLK
host->host_caps |= MMC_MODE_8BIT;
#ifndef CONFIG_BLK
- return add_sdhci(host, 52000000, 400000);
+ return add_sdhci(host, 0, 400000);
- ret = sdhci_setup_cfg(&plat->cfg, host, 52000000, 400000);
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0, 400000);
*/
if (host->clk_mul) {
for (div = 1; div <= 1024; div++) {
*/
if (host->clk_mul) {
for (div = 1; div <= 1024; div++) {
- if ((mmc->cfg->f_max * host->clk_mul / div)
+ if ((host->max_clk * host->clk_mul / div)
div--;
} else {
/* Version 3.00 divisors must be a multiple of 2. */
div--;
} else {
/* Version 3.00 divisors must be a multiple of 2. */
- if (mmc->cfg->f_max <= clock) {
+ if (host->max_clk <= clock) {
div = 1;
} else {
for (div = 2;
div < SDHCI_MAX_DIV_SPEC_300;
div += 2) {
div = 1;
} else {
for (div = 2;
div < SDHCI_MAX_DIV_SPEC_300;
div += 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ if ((host->max_clk / div) <= clock)
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
} else {
/* Version 2.00 divisors must be a power of 2. */
for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
- if ((mmc->cfg->f_max / div) <= clock)
+ if ((host->max_clk / div) <= clock)
#endif
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
#endif
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
- u32 max_clk, u32 min_clk)
#ifndef CONFIG_DM_MMC_OPS
cfg->ops = &sdhci_ops;
#endif
#ifndef CONFIG_DM_MMC_OPS
cfg->ops = &sdhci_ops;
#endif
- if (max_clk)
- cfg->f_max = max_clk;
- else {
+ if (host->max_clk == 0) {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
- cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
+ host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
SDHCI_CLOCK_BASE_SHIFT;
else
SDHCI_CLOCK_BASE_SHIFT;
else
- cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >>
+ host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
+ host->max_clk *= 1000000;
+ if (host->max_clk == 0) {
printf("%s: Hardware doesn't specify base clock frequency\n",
__func__);
return -EINVAL;
}
printf("%s: Hardware doesn't specify base clock frequency\n",
__func__);
return -EINVAL;
}
- if (min_clk)
- cfg->f_min = min_clk;
+ if (f_max && (f_max < host->max_clk))
+ cfg->f_max = f_max;
+ else
+ cfg->f_max = host->max_clk;
+ if (f_min)
+ cfg->f_min = f_min;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
else {
if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
return mmc_bind(dev, mmc, cfg);
}
#else
return mmc_bind(dev, mmc, cfg);
}
#else
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
- ret = sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk);
+ ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
#endif
- ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ,
+ host->max_clk = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
+
+ ret = sdhci_setup_cfg(&plat->cfg, host, 0,
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
CONFIG_ZYNQ_SDHCI_MIN_FREQ);
host->mmc = &plat->mmc;
if (ret)
unsigned int quirks;
unsigned int host_caps;
unsigned int version;
unsigned int quirks;
unsigned int host_caps;
unsigned int version;
+ unsigned int max_clk; /* Maximum Base Clock frequency */
unsigned int clk_mul; /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
unsigned int clk_mul; /* Clock Multiplier value */
unsigned int clock;
struct mmc *mmc;
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
* @host: SDHCI host structure
*
* @cfg: Configuration structure to fill in (generally &plat->mmc)
* @host: SDHCI host structure
- * @max_clk: Maximum supported clock speed in HZ (0 for default)
- * @min_clk: Minimum supported clock speed in HZ (0 for default)
+ * @f_max: Maximum supported clock frequency in HZ (0 for default)
+ * @f_min: Minimum supported clock frequency in HZ (0 for default)
*/
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
*/
int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
- u32 max_clk, u32 min_clk);
/**
* sdhci_bind() - Set up a new MMC block device
/**
* sdhci_bind() - Set up a new MMC block device
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
* @host: SDHCI host structure
* This is used when you are not using CONFIG_BLK. Convert your driver over!
*
* @host: SDHCI host structure
- * @max_clk: Maximum supported clock speed in HZ (0 for default)
- * @min_clk: Minimum supported clock speed in HZ (0 for default)
+ * @f_max: Maximum supported clock frequency in HZ (0 for default)
+ * @f_min: Minimum supported clock frequency in HZ (0 for default)
* @return 0 if OK, -ve on error
*/
* @return 0 if OK, -ve on error
*/
-int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
+int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
#endif /* !CONFIG_BLK */
#ifdef CONFIG_DM_MMC_OPS
#endif /* !CONFIG_BLK */
#ifdef CONFIG_DM_MMC_OPS