Enabled both DDR clock signals to support Clearfog variants (currently,
Clearfog GTR) that need both clocks.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
BUS_MASK_32BIT, /* Busses mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
{ {0} }, /* raw spd data */
- {0} /* timing parameters */
+ {0}, /* timing parameters */
+ { {0} }, /* electrical configuration */
+ {0,}, /* electrical parameters */
+ 0x3, /* clock enable mask */
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
};
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)