+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ int data = 0, div = 0, offset = 0;
+
+ if (!clock_id_is_pll(clkid))
+ return -1;
+
+ if (pllout + 1 > pll_num_clkouts[clkid])
+ return -1;
+
+ div = clk_get_divider(8, pll_rate[clkid], rate);
+
+ if (div < 0)
+ return -1;
+
+ /* out2 and out4 are in the high part of the register */
+ if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+ offset = 16;
+
+ data = (div << PLL_OUT_RATIO_SHIFT) |
+ PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+ clrsetbits_le32(&pll->pll_out[pllout >> 1],
+ PLL_OUT_RATIO_MASK << offset, data << offset);
+
+ return 0;
+}
+