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ARM: DRA7xx: Change clk divider setting
author
Lokesh Vutla
<lokeshvutla@ti.com>
Thu, 12 Dec 2013 10:04:56 +0000
(15:34 +0530)
committer
Tom Rini
<trini@ti.com>
Thu, 12 Dec 2013 22:43:39 +0000
(17:43 -0500)
Commit "armv7: hw_data: change clock divider setting"
updates the setting for m6 divider for 20MHz sys_clk frequency.
But missed to update for other sys_clk frequencies. Doing the same.
Reported-by: Rajendran, Vinothkumar <vinothr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
arch/arm/cpu/armv7/omap5/hw_data.c
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diff --git
a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index 82910e87a03c128adf0f8b843750fff7281787f3..a0d69a723d2a5a52dfbad25464f3064de5b3217d 100644
(file)
--- a/
arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/
arch/arm/cpu/armv7/omap5/hw_data.c
@@
-169,13
+169,13
@@
static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
};
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
- {32, 0, 4, 1, 3, 4,
10, 2, -1, -1, -1, -1},
/* 12 MHz */
+ {32, 0, 4, 1, 3, 4,
4, 2, -1, -1, -1, -1},
/* 12 MHz */
{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
{96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
- {160, 6, 4, 1, 3, 4,
10, 2, -1, -1, -1, -1},
/* 16.8 MHz */
- {20, 0, 4, 1, 3, 4,
10, 2, -1, -1, -1, -1},
/* 19.2 MHz */
- {192, 12, 4, 1, 3, 4,
10, 2, -1, -1, -1, -1},
/* 26 MHz */
+ {160, 6, 4, 1, 3, 4,
4, 2, -1, -1, -1, -1},
/* 16.8 MHz */
+ {20, 0, 4, 1, 3, 4,
4, 2, -1, -1, -1, -1},
/* 19.2 MHz */
+ {192, 12, 4, 1, 3, 4,
4, 2, -1, -1, -1, -1},
/* 26 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
- {10, 0, 4, 1, 3, 4,
10, 2, -1, -1, -1, -1},
/* 38.4 MHz */
+ {10, 0, 4, 1, 3, 4,
4, 2, -1, -1, -1, -1},
/* 38.4 MHz */
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
};
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {