-#define SWCRR 0x0204 /* Register offset to immr */
-#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */
-#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */
-#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */
-#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */
-#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
-
-/* SWCNR - System Watchdog Counter Register
+/* Register offset to immr */
+#define SWCRR 0x0204
+/* Software Watchdog Time Count */
+#define SWCRR_SWTC 0xFFFF0000
+/* Watchdog Enable bit */
+#define SWCRR_SWEN 0x00000004
+/* Software Watchdog Reset/Interrupt Select bit */
+#define SWCRR_SWRI 0x00000002
+/* Software Watchdog Counter Prescale bit */
+#define SWCRR_SWPR 0x00000001
+#define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
+ SWCRR_SWRI | SWCRR_SWPR))
+
+/*
+ * SWCNR - System Watchdog Counter Register