-+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
-+#define FLASHCTL_IDCY_S 0
-+#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
-+#define FLASHCTL_WST1_S 5
-+#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
-+#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
-+#define FLASHCTL_WST2_S 11
-+#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
-+#define FLASHCTL_AC_S 16
-+#define FLASHCTL_AC_128K 0x00000000
-+#define FLASHCTL_AC_256K 0x00010000
-+#define FLASHCTL_AC_512K 0x00020000
-+#define FLASHCTL_AC_1M 0x00030000
-+#define FLASHCTL_AC_2M 0x00040000
-+#define FLASHCTL_AC_4M 0x00050000
-+#define FLASHCTL_AC_8M 0x00060000
-+#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
-+#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
-+#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
-+#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
-+#define FLASHCTL_WP 0x04000000 /* Write protect */
-+#define FLASHCTL_BM 0x08000000 /* Burst mode */
-+#define FLASHCTL_MW 0x30000000 /* Memory width */
-+#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
-+#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
-+#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
-+#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
-+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
-+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
++#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
++#define AR5312_FLASHCTL_IDCY_S 0
++#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
++#define AR5312_FLASHCTL_WST1_S 5
++#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
++#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
++#define AR5312_FLASHCTL_WST2_S 11
++#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
++#define AR5312_FLASHCTL_AC_S 16
++#define AR5312_FLASHCTL_AC_128K 0x00000000
++#define AR5312_FLASHCTL_AC_256K 0x00010000
++#define AR5312_FLASHCTL_AC_512K 0x00020000
++#define AR5312_FLASHCTL_AC_1M 0x00030000
++#define AR5312_FLASHCTL_AC_2M 0x00040000
++#define AR5312_FLASHCTL_AC_4M 0x00050000
++#define AR5312_FLASHCTL_AC_8M 0x00060000
++#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
++#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
++#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
++#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
++#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
++#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
++#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
++#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
++#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
++#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
++#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
++#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
++#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */