-+#ifndef PCI_DMA_TODEVICE
-+#define PCI_DMA_TODEVICE 1
-+#define PCI_DMA_FROMDEVICE 2
-+#endif
-+
-+typedef u32 dma_addr_t;
-+
-+/* Pure 2^n version of get_order */
-+static inline int get_order(unsigned long size)
-+{
-+ int order;
-+
-+ size = (size-1) >> (PAGE_SHIFT-1);
-+ order = -1;
-+ do {
-+ size >>= 1;
-+ order++;
-+ } while (size);
-+ return order;
-+}
-+
-+static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
-+ dma_addr_t *dma_handle)
-+{
-+ void *ret;
-+ int gfp = GFP_ATOMIC | GFP_DMA;
-+
-+ ret = (void *)__get_free_pages(gfp, get_order(size));
-+
-+ if (ret != NULL) {
-+ memset(ret, 0, size);
-+ *dma_handle = virt_to_bus(ret);
-+ }
-+ return ret;
-+}
-+static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
-+ void *vaddr, dma_addr_t dma_handle)
-+{
-+ free_pages((unsigned long)vaddr, get_order(size));
-+}
-+#ifdef ILSIM
-+extern uint pci_map_single(void *dev, void *va, uint size, int direction);
-+extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
-+#else
-+#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
-+#define pci_unmap_single(cookie, address, size, dir)
-+#endif
-+
-+#endif /* DMA mapping */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
-+
-+#define dev_kfree_skb_any(a) dev_kfree_skb(a)
-+#define netif_down(dev) do { (dev)->start = 0; } while(0)
-+
-+/* pcmcia-cs provides its own netdevice compatibility layer */
-+#ifndef _COMPAT_NETDEVICE_H
-+
-+/*
-+ * SoftNet
-+ *
-+ * For pre-softnet kernels we need to tell the upper layer not to
-+ * re-enter start_xmit() while we are in there. However softnet
-+ * guarantees not to enter while we are in there so there is no need
-+ * to do the netif_stop_queue() dance unless the transmit queue really
-+ * gets stuck. This should also improve performance according to tests
-+ * done by Aman Singla.
-+ */
-+
-+#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
-+#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
-+#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
-+
-+static inline void netif_start_queue(struct net_device *dev)
-+{
-+ dev->tbusy = 0;
-+ dev->interrupt = 0;
-+ dev->start = 1;
-+}
-+
-+#define netif_queue_stopped(dev) (dev)->tbusy
-+#define netif_running(dev) (dev)->start
-+
-+#endif /* _COMPAT_NETDEVICE_H */
-+
-+#define netif_device_attach(dev) netif_start_queue(dev)
-+#define netif_device_detach(dev) netif_stop_queue(dev)
-+
-+/* 2.4.x renamed bottom halves to tasklets */
-+#define tasklet_struct tq_struct
-+static inline void tasklet_schedule(struct tasklet_struct *tasklet)
-+{
-+ queue_task(tasklet, &tq_immediate);
-+ mark_bh(IMMEDIATE_BH);
-+}
-+
-+static inline void tasklet_init(struct tasklet_struct *tasklet,
-+ void (*func)(unsigned long),
-+ unsigned long data)
-+{
-+ tasklet->next = NULL;
-+ tasklet->sync = 0;
-+ tasklet->routine = (void (*)(void *))func;
-+ tasklet->data = (void *)data;
-+}
-+#define tasklet_kill(tasklet) {do{} while(0);}
-+
-+/* 2.4.x introduced del_timer_sync() */
-+#define del_timer_sync(timer) del_timer(timer)
-+
-+#else
-+
-+#define netif_down(dev)
-+
-+#endif /* SoftNet */
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
-+
-+/*
-+ * Emit code to initialise a tq_struct's routine and data pointers
-+ */
-+#define PREPARE_TQUEUE(_tq, _routine, _data) \
-+ do { \
-+ (_tq)->routine = _routine; \
-+ (_tq)->data = _data; \
-+ } while (0)
-+
-+/*
-+ * Emit code to initialise all of a tq_struct
-+ */
-+#define INIT_TQUEUE(_tq, _routine, _data) \
-+ do { \
-+ INIT_LIST_HEAD(&(_tq)->list); \
-+ (_tq)->sync = 0; \
-+ PREPARE_TQUEUE((_tq), (_routine), (_data)); \
-+ } while (0)
-+
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
-+
-+/* Power management related routines */
-+
-+static inline int
-+pci_save_state(struct pci_dev *dev, u32 *buffer)
-+{
-+ int i;
-+ if (buffer) {
-+ for (i = 0; i < 16; i++)
-+ pci_read_config_dword(dev, i * 4,&buffer[i]);
-+ }
-+ return 0;
-+}
-+
-+static inline int
-+pci_restore_state(struct pci_dev *dev, u32 *buffer)
-+{
-+ int i;
-+
-+ if (buffer) {
-+ for (i = 0; i < 16; i++)
-+ pci_write_config_dword(dev,i * 4, buffer[i]);
-+ }
-+ /*
-+ * otherwise, write the context information we know from bootup.
-+ * This works around a problem where warm-booting from Windows
-+ * combined with a D3(hot)->D0 transition causes PCI config
-+ * header data to be forgotten.
-+ */
-+ else {
-+ for (i = 0; i < 6; i ++)
-+ pci_write_config_dword(dev,
-+ PCI_BASE_ADDRESS_0 + (i * 4),
-+ pci_resource_start(dev, i));
-+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-+ }
-+ return 0;
-+}
-+
-+#endif /* PCI power management */
-+
-+/* Old cp0 access macros deprecated in 2.4.19 */
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
-+#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
-+#endif
-+
-+/* Module refcount handled internally in 2.6.x */
-+#ifndef SET_MODULE_OWNER
-+#define SET_MODULE_OWNER(dev) do {} while (0)
-+#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
-+#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
-+#else
-+#define OLD_MOD_INC_USE_COUNT do {} while (0)
-+#define OLD_MOD_DEC_USE_COUNT do {} while (0)
-+#endif
-+
-+#ifndef SET_NETDEV_DEV
-+#define SET_NETDEV_DEV(net, pdev) do {} while (0)
-+#endif
-+
-+#ifndef HAVE_FREE_NETDEV
-+#define free_netdev(dev) kfree(dev)
-+#endif
-+
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
-+/* struct packet_type redefined in 2.6.x */
-+#define af_packet_priv data
-+#endif
-+
-+#endif /* _linuxver_h_ */
-diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h
---- linux-2.4.32/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/min_osl.h 2005-12-16 23:39:10.748824500 +0100
-@@ -0,0 +1,126 @@
-+/*
-+ * HND Minimal OS Abstraction Layer.
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _min_osl_h_
-+#define _min_osl_h_
-+
-+#include <typedefs.h>
-+#include <sbconfig.h>
-+#include <mipsinc.h>
-+
-+/* Cache support */
-+extern void caches_on(void);
-+extern void blast_dcache(void);
-+extern void blast_icache(void);
-+
-+/* uart output */
-+extern void putc(int c);
-+
-+/* lib functions */
-+extern int printf(const char *fmt, ...);
-+extern int sprintf(char *buf, const char *fmt, ...);
-+extern int strcmp(const char *s1, const char *s2);
-+extern int strncmp(const char *s1, const char *s2, uint n);
-+extern char *strcpy(char *dest, const char *src);
-+extern char *strncpy(char *dest, const char *src, uint n);
-+extern uint strlen(const char *s);
-+extern char *strchr(const char *str,int c);
-+extern char *strrchr(const char *str, int c);
-+extern char *strcat(char *d, const char *s);
-+extern void *memset(void *dest, int c, uint n);
-+extern void *memcpy(void *dest, const void *src, uint n);
-+extern int memcmp(const void *s1, const void *s2, uint n);
-+#define bcopy(src, dst, len) memcpy((dst), (src), (len))
-+#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
-+#define bzero(b, len) memset((b), '\0', (len))
-+
-+/* assert & debugging */
-+#define ASSERT(exp) do {} while (0)
-+
-+/* PCMCIA attribute space access macros */
-+#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
-+ ASSERT(0)
-+#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
-+ ASSERT(0)
-+
-+/* PCI configuration space access macros */
-+#define OSL_PCI_READ_CONFIG(loc, offset, size) \
-+ (offset == 8 ? 0 : 0xffffffff)
-+#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
-+ do {} while (0)
-+
-+/* PCI device bus # and slot # */
-+#define OSL_PCI_BUS(osh) (0)
-+#define OSL_PCI_SLOT(osh) (0)
-+
-+/* register access macros */
-+#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
-+#define rreg32(r) (*(volatile uint32*)(r))
-+#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
-+#define rreg16(r) (*(volatile uint16*)(r))
-+#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
-+#define rreg8(r) (*(volatile uint8*)(r))
-+#define R_REG(r) ({ \
-+ __typeof(*(r)) __osl_v; \
-+ switch (sizeof(*(r))) { \
-+ case sizeof(uint8): __osl_v = rreg8((r)); break; \
-+ case sizeof(uint16): __osl_v = rreg16((r)); break; \
-+ case sizeof(uint32): __osl_v = rreg32((r)); break; \
-+ } \
-+ __osl_v; \
-+})
-+#define W_REG(r, v) do { \
-+ switch (sizeof(*(r))) { \
-+ case sizeof(uint8): wreg8((r), (v)); break; \
-+ case sizeof(uint16): wreg16((r), (v)); break; \
-+ case sizeof(uint32): wreg32((r), (v)); break; \
-+ } \
-+} while (0)
-+#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
-+#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
-+
-+/* general purpose memory allocation */
-+#define MALLOC(osh, size) malloc(size)
-+#define MFREE(osh, addr, size) free(addr)
-+#define MALLOCED(osh) 0
-+#define MALLOC_FAILED(osh) 0
-+#define MALLOC_DUMP(osh, buf, sz)
-+extern int free(void *ptr);
-+extern void *malloc(uint size);
-+
-+/* uncached virtual address */
-+#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
-+
-+/* host/bus architecture-specific address byte swap */
-+#define BUS_SWAP32(v) (v)
-+
-+/* microsecond delay */
-+#define OSL_DELAY(usec) udelay(usec)
-+extern void udelay(uint32 usec);
-+
-+/* map/unmap physical to virtual I/O */
-+#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
-+#define REG_UNMAP(va) do {} while (0)
-+
-+/* dereference an address that may cause a bus exception */
-+#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
-+
-+/* Misc stubs */
-+#define osl_attach(pdev) ((osl_t*)pdev)
-+#define osl_detach(osh)
-+extern void *osl_init(void);
-+#define OSL_ERROR(bcmerror) osl_error(bcmerror)
-+extern int osl_error(int);
-+
-+#endif /* _min_osl_h_ */
-diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h
---- linux-2.4.32/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/mipsinc.h 2005-12-16 23:39:10.748824500 +0100
-@@ -0,0 +1,552 @@
-+/*
-+ * HND Run Time Environment for standalone MIPS programs.
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _MISPINC_H
-+#define _MISPINC_H
-+
-+
-+/* MIPS defines */
-+
-+#ifdef _LANGUAGE_ASSEMBLY
-+
-+/*
-+ * Symbolic register names for 32 bit ABI
-+ */
-+#define zero $0 /* wired zero */
-+#define AT $1 /* assembler temp - uppercase because of ".set at" */
-+#define v0 $2 /* return value */
-+#define v1 $3
-+#define a0 $4 /* argument registers */
-+#define a1 $5
-+#define a2 $6
-+#define a3 $7
-+#define t0 $8 /* caller saved */
-+#define t1 $9
-+#define t2 $10
-+#define t3 $11
-+#define t4 $12
-+#define t5 $13
-+#define t6 $14
-+#define t7 $15
-+#define s0 $16 /* callee saved */
-+#define s1 $17
-+#define s2 $18
-+#define s3 $19
-+#define s4 $20
-+#define s5 $21
-+#define s6 $22
-+#define s7 $23
-+#define t8 $24 /* caller saved */
-+#define t9 $25
-+#define jp $25 /* PIC jump register */
-+#define k0 $26 /* kernel scratch */
-+#define k1 $27
-+#define gp $28 /* global pointer */
-+#define sp $29 /* stack pointer */
-+#define fp $30 /* frame pointer */
-+#define s8 $30 /* same like fp! */
-+#define ra $31 /* return address */
-+
-+
-+/*
-+ * CP0 Registers
-+ */
-+
-+#define C0_INX $0
-+#define C0_RAND $1
-+#define C0_TLBLO0 $2
-+#define C0_TLBLO C0_TLBLO0
-+#define C0_TLBLO1 $3
-+#define C0_CTEXT $4
-+#define C0_PGMASK $5
-+#define C0_WIRED $6
-+#define C0_BADVADDR $8
-+#define C0_COUNT $9
-+#define C0_TLBHI $10
-+#define C0_COMPARE $11
-+#define C0_SR $12
-+#define C0_STATUS C0_SR
-+#define C0_CAUSE $13
-+#define C0_EPC $14
-+#define C0_PRID $15
-+#define C0_CONFIG $16
-+#define C0_LLADDR $17
-+#define C0_WATCHLO $18
-+#define C0_WATCHHI $19
-+#define C0_XCTEXT $20
-+#define C0_DIAGNOSTIC $22
-+#define C0_BROADCOM C0_DIAGNOSTIC
-+#define C0_PERFORMANCE $25
-+#define C0_ECC $26
-+#define C0_CACHEERR $27
-+#define C0_TAGLO $28
-+#define C0_TAGHI $29
-+#define C0_ERREPC $30
-+#define C0_DESAVE $31
-+
-+/*
-+ * LEAF - declare leaf routine
-+ */
-+#define LEAF(symbol) \
-+ .globl symbol; \
-+ .align 2; \
-+ .type symbol,@function; \
-+ .ent symbol,0; \
-+symbol: .frame sp,0,ra
-+
-+/*
-+ * END - mark end of function
-+ */
-+#define END(function) \
-+ .end function; \
-+ .size function,.-function
-+
-+#define _ULCAST_
-+
-+#else
-+
-+/*
-+ * The following macros are especially useful for __asm__
-+ * inline assembler.
-+ */
-+#ifndef __STR
-+#define __STR(x) #x
-+#endif
-+#ifndef STR
-+#define STR(x) __STR(x)
-+#endif
-+
-+#define _ULCAST_ (unsigned long)
-+
-+
-+/*
-+ * CP0 Registers
-+ */
-+
-+#define C0_INX 0 /* CP0: TLB Index */
-+#define C0_RAND 1 /* CP0: TLB Random */
-+#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
-+#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
-+#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
-+#define C0_CTEXT 4 /* CP0: Context */
-+#define C0_PGMASK 5 /* CP0: TLB PageMask */
-+#define C0_WIRED 6 /* CP0: TLB Wired */
-+#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
-+#define C0_COUNT 9 /* CP0: Count */
-+#define C0_TLBHI 10 /* CP0: TLB EntryHi */
-+#define C0_COMPARE 11 /* CP0: Compare */
-+#define C0_SR 12 /* CP0: Processor Status */
-+#define C0_STATUS C0_SR /* CP0: Processor Status */
-+#define C0_CAUSE 13 /* CP0: Exception Cause */
-+#define C0_EPC 14 /* CP0: Exception PC */
-+#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
-+#define C0_CONFIG 16 /* CP0: Config */
-+#define C0_LLADDR 17 /* CP0: LLAddr */
-+#define C0_WATCHLO 18 /* CP0: WatchpointLo */
-+#define C0_WATCHHI 19 /* CP0: WatchpointHi */
-+#define C0_XCTEXT 20 /* CP0: XContext */
-+#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
-+#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
-+#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
-+#define C0_ECC 26 /* CP0: ECC */
-+#define C0_CACHEERR 27 /* CP0: CacheErr */
-+#define C0_TAGLO 28 /* CP0: TagLo */
-+#define C0_TAGHI 29 /* CP0: TagHi */
-+#define C0_ERREPC 30 /* CP0: ErrorEPC */
-+#define C0_DESAVE 31 /* CP0: DebugSave */
-+
-+#endif /* _LANGUAGE_ASSEMBLY */
-+
-+/*
-+ * Memory segments (32bit kernel mode addresses)
-+ */
-+#undef KUSEG
-+#undef KSEG0
-+#undef KSEG1
-+#undef KSEG2
-+#undef KSEG3
-+#define KUSEG 0x00000000
-+#define KSEG0 0x80000000
-+#define KSEG1 0xa0000000
-+#define KSEG2 0xc0000000
-+#define KSEG3 0xe0000000
-+#define PHYSADDR_MASK 0x1fffffff
-+
-+/*
-+ * Map an address to a certain kernel segment
-+ */
-+#undef PHYSADDR
-+#undef KSEG0ADDR
-+#undef KSEG1ADDR
-+#undef KSEG2ADDR
-+#undef KSEG3ADDR
-+
-+#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
-+#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
-+#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
-+#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
-+#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
-+
-+
-+#ifndef Index_Invalidate_I
-+/*
-+ * Cache Operations
-+ */
-+#define Index_Invalidate_I 0x00
-+#define Index_Writeback_Inv_D 0x01
-+#define Index_Invalidate_SI 0x02
-+#define Index_Writeback_Inv_SD 0x03
-+#define Index_Load_Tag_I 0x04
-+#define Index_Load_Tag_D 0x05
-+#define Index_Load_Tag_SI 0x06
-+#define Index_Load_Tag_SD 0x07
-+#define Index_Store_Tag_I 0x08
-+#define Index_Store_Tag_D 0x09
-+#define Index_Store_Tag_SI 0x0A
-+#define Index_Store_Tag_SD 0x0B
-+#define Create_Dirty_Excl_D 0x0d
-+#define Create_Dirty_Excl_SD 0x0f
-+#define Hit_Invalidate_I 0x10
-+#define Hit_Invalidate_D 0x11
-+#define Hit_Invalidate_SI 0x12
-+#define Hit_Invalidate_SD 0x13
-+#define Fill_I 0x14
-+#define Hit_Writeback_Inv_D 0x15
-+ /* 0x16 is unused */
-+#define Hit_Writeback_Inv_SD 0x17
-+#define R5K_Page_Invalidate_S 0x17
-+#define Hit_Writeback_I 0x18
-+#define Hit_Writeback_D 0x19
-+ /* 0x1a is unused */
-+#define Hit_Writeback_SD 0x1b
-+ /* 0x1c is unused */
-+ /* 0x1e is unused */
-+#define Hit_Set_Virtual_SI 0x1e
-+#define Hit_Set_Virtual_SD 0x1f
-+#endif
-+
-+
-+/*
-+ * R4x00 interrupt enable / cause bits
-+ */
-+#define IE_SW0 (_ULCAST_(1) << 8)
-+#define IE_SW1 (_ULCAST_(1) << 9)
-+#define IE_IRQ0 (_ULCAST_(1) << 10)
-+#define IE_IRQ1 (_ULCAST_(1) << 11)
-+#define IE_IRQ2 (_ULCAST_(1) << 12)
-+#define IE_IRQ3 (_ULCAST_(1) << 13)
-+#define IE_IRQ4 (_ULCAST_(1) << 14)
-+#define IE_IRQ5 (_ULCAST_(1) << 15)
-+
-+#ifndef ST0_UM
-+/*
-+ * Bitfields in the mips32 cp0 status register
-+ */
-+#define ST0_IE 0x00000001
-+#define ST0_EXL 0x00000002
-+#define ST0_ERL 0x00000004
-+#define ST0_UM 0x00000010
-+#define ST0_SWINT0 0x00000100
-+#define ST0_SWINT1 0x00000200
-+#define ST0_HWINT0 0x00000400
-+#define ST0_HWINT1 0x00000800
-+#define ST0_HWINT2 0x00001000
-+#define ST0_HWINT3 0x00002000
-+#define ST0_HWINT4 0x00004000
-+#define ST0_HWINT5 0x00008000
-+#define ST0_IM 0x0000ff00
-+#define ST0_NMI 0x00080000
-+#define ST0_SR 0x00100000
-+#define ST0_TS 0x00200000
-+#define ST0_BEV 0x00400000
-+#define ST0_RE 0x02000000
-+#define ST0_RP 0x08000000
-+#define ST0_CU 0xf0000000
-+#define ST0_CU0 0x10000000
-+#define ST0_CU1 0x20000000
-+#define ST0_CU2 0x40000000
-+#define ST0_CU3 0x80000000
-+#endif
-+
-+
-+/*
-+ * Bitfields in the mips32 cp0 cause register
-+ */
-+#define C_EXC 0x0000007c
-+#define C_EXC_SHIFT 2
-+#define C_INT 0x0000ff00
-+#define C_INT_SHIFT 8
-+#define C_SW0 (_ULCAST_(1) << 8)
-+#define C_SW1 (_ULCAST_(1) << 9)
-+#define C_IRQ0 (_ULCAST_(1) << 10)
-+#define C_IRQ1 (_ULCAST_(1) << 11)
-+#define C_IRQ2 (_ULCAST_(1) << 12)
-+#define C_IRQ3 (_ULCAST_(1) << 13)
-+#define C_IRQ4 (_ULCAST_(1) << 14)
-+#define C_IRQ5 (_ULCAST_(1) << 15)
-+#define C_WP 0x00400000
-+#define C_IV 0x00800000
-+#define C_CE 0x30000000
-+#define C_CE_SHIFT 28
-+#define C_BD 0x80000000
-+
-+/* Values in C_EXC */
-+#define EXC_INT 0
-+#define EXC_TLBM 1
-+#define EXC_TLBL 2
-+#define EXC_TLBS 3
-+#define EXC_AEL 4
-+#define EXC_AES 5
-+#define EXC_IBE 6
-+#define EXC_DBE 7
-+#define EXC_SYS 8
-+#define EXC_BPT 9
-+#define EXC_RI 10
-+#define EXC_CU 11
-+#define EXC_OV 12
-+#define EXC_TR 13
-+#define EXC_WATCH 23
-+#define EXC_MCHK 24
-+
-+
-+/*
-+ * Bits in the cp0 config register.
-+ */
-+#define CONF_CM_CACHABLE_NO_WA 0
-+#define CONF_CM_CACHABLE_WA 1
-+#define CONF_CM_UNCACHED 2
-+#define CONF_CM_CACHABLE_NONCOHERENT 3
-+#define CONF_CM_CACHABLE_CE 4
-+#define CONF_CM_CACHABLE_COW 5
-+#define CONF_CM_CACHABLE_CUW 6
-+#define CONF_CM_CACHABLE_ACCELERATED 7
-+#define CONF_CM_CMASK 7
-+#define CONF_CU (_ULCAST_(1) << 3)
-+#define CONF_DB (_ULCAST_(1) << 4)
-+#define CONF_IB (_ULCAST_(1) << 5)
-+#define CONF_SE (_ULCAST_(1) << 12)
-+#define CONF_SC (_ULCAST_(1) << 17)
-+#define CONF_AC (_ULCAST_(1) << 23)
-+#define CONF_HALT (_ULCAST_(1) << 25)
-+
-+
-+/*
-+ * Bits in the cp0 config register select 1.
-+ */
-+#define CONF1_FP 0x00000001 /* FPU present */
-+#define CONF1_EP 0x00000002 /* EJTAG present */
-+#define CONF1_CA 0x00000004 /* mips16 implemented */
-+#define CONF1_WR 0x00000008 /* Watch registers present */
-+#define CONF1_PC 0x00000010 /* Performance counters present */
-+#define CONF1_DA_SHIFT 7 /* D$ associativity */
-+#define CONF1_DA_MASK 0x00000380
-+#define CONF1_DA_BASE 1
-+#define CONF1_DL_SHIFT 10 /* D$ line size */
-+#define CONF1_DL_MASK 0x00001c00
-+#define CONF1_DL_BASE 2
-+#define CONF1_DS_SHIFT 13 /* D$ sets/way */
-+#define CONF1_DS_MASK 0x0000e000
-+#define CONF1_DS_BASE 64
-+#define CONF1_IA_SHIFT 16 /* I$ associativity */
-+#define CONF1_IA_MASK 0x00070000
-+#define CONF1_IA_BASE 1
-+#define CONF1_IL_SHIFT 19 /* I$ line size */
-+#define CONF1_IL_MASK 0x00380000
-+#define CONF1_IL_BASE 2
-+#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
-+#define CONF1_IS_MASK 0x01c00000
-+#define CONF1_IS_BASE 64
-+#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
-+#define CONF1_MS_SHIFT 25
-+
-+/* PRID register */
-+#define PRID_COPT_MASK 0xff000000
-+#define PRID_COMP_MASK 0x00ff0000
-+#define PRID_IMP_MASK 0x0000ff00
-+#define PRID_REV_MASK 0x000000ff
-+
-+#define PRID_COMP_LEGACY 0x000000
-+#define PRID_COMP_MIPS 0x010000
-+#define PRID_COMP_BROADCOM 0x020000
-+#define PRID_COMP_ALCHEMY 0x030000
-+#define PRID_COMP_SIBYTE 0x040000
-+#define PRID_IMP_BCM4710 0x4000
-+#define PRID_IMP_BCM3302 0x9000
-+#define PRID_IMP_BCM3303 0x9100
-+
-+#define PRID_IMP_UNKNOWN 0xff00
-+
-+#define BCM330X(id) \
-+ (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
-+ || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
-+
-+/* Bits in C0_BROADCOM */
-+#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
-+#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
-+#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
-+#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
-+
-+/* PreFetch Cache aka Read Ahead Cache */
-+
-+#define PFC_CR0 0xff400000 /* control reg 0 */
-+#define PFC_CR1 0xff400004 /* control reg 1 */
-+
-+/* PFC operations */
-+#define PFC_I 0x00000001 /* Enable PFC use for instructions */
-+#define PFC_D 0x00000002 /* Enable PFC use for data */
-+#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
-+#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
-+#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
-+#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
-+#define PFC_DPF 0x00000040 /* Enable directional prefetching */
-+#define PFC_FLUSH 0x00000100 /* Flush the PFC */
-+#define PFC_BRR 0x40000000 /* Bus error indication */
-+#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
-+
-+/* Handy defaults */
-+#define PFC_DISABLED 0
-+#define PFC_AUTO 0xffffffff /* auto select the default mode */
-+#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
-+#define PFC_INST_NOPF (PFC_I | PFC_CINV)
-+#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
-+#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
-+#define PFC_I_AND_D (PFC_INST | PFC_DATA)
-+#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
-+
-+
-+/*
-+ * These are the UART port assignments, expressed as offsets from the base
-+ * register. These assignments should hold for any serial port based on
-+ * a 8250, 16450, or 16550(A).
-+ */
-+
-+#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
-+#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
-+#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
-+#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
-+#define UART_LCR 3 /* Out: Line Control Register */
-+#define UART_MCR 4 /* Out: Modem Control Register */
-+#define UART_LSR 5 /* In: Line Status Register */
-+#define UART_MSR 6 /* In: Modem Status Register */
-+#define UART_SCR 7 /* I/O: Scratch Register */
-+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-+#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
-+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
-+#define UART_LSR_RXRDY 0x01 /* Receiver ready */
-+
-+
-+#ifndef _LANGUAGE_ASSEMBLY
-+
-+/*
-+ * Macros to access the system control coprocessor
-+ */
-+
-+#define MFC0(source, sel) \
-+({ \
-+ int __res; \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
-+ "move\t%0,$1\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ :"=r" (__res) \
-+ : \
-+ :"$1"); \
-+ __res; \
-+})
-+
-+#define MTC0(source, sel, value) \
-+do { \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ "move\t$1,%z0\n\t" \
-+ ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ : \
-+ :"jr" (value) \
-+ :"$1"); \
-+} while (0)
-+
-+#define get_c0_count() \
-+({ \
-+ int __res; \
-+ __asm__ __volatile__( \
-+ ".set\tnoreorder\n\t" \
-+ ".set\tnoat\n\t" \
-+ "mfc0\t%0,$9\n\t" \
-+ ".set\tat\n\t" \
-+ ".set\treorder" \
-+ :"=r" (__res)); \
-+ __res; \
-+})
-+
-+static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
-+{
-+ uint lsz, sets, ways;
-+
-+ /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
-+ if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
-+ lsz = CONF1_IL_BASE << lsz;
-+ sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
-+ ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
-+ *size = lsz * sets * ways;
-+ *lsize = lsz;
-+}
-+
-+static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
-+{
-+ uint lsz, sets, ways;
-+
-+ /* Data Cache Size = Associativity * Line Size * Sets Per Way */
-+ if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
-+ lsz = CONF1_DL_BASE << lsz;
-+ sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
-+ ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
-+ *size = lsz * sets * ways;
-+ *lsize = lsz;
-+}
-+
-+#define cache_op(base, op) \
-+ __asm__ __volatile__(" \
-+ .set noreorder; \
-+ .set mips3; \
-+ cache %1, (%0); \
-+ .set mips0; \
-+ .set reorder" \
-+ : \
-+ : "r" (base), \
-+ "i" (op));
-+
-+#define cache_unroll4(base, delta, op) \
-+ __asm__ __volatile__(" \
-+ .set noreorder; \
-+ .set mips3; \
-+ cache %1,0(%0); \
-+ cache %1,delta(%0); \
-+ cache %1,(2 * delta)(%0); \
-+ cache %1,(3 * delta)(%0); \
-+ .set mips0; \
-+ .set reorder" \
-+ : \
-+ : "r" (base), \
-+ "i" (op));
-+
-+#endif /* !_LANGUAGE_ASSEMBLY */
-+
-+#endif /* _MISPINC_H */
-diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/nvports.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h
---- linux-2.4.32/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/nvports.h 2005-12-16 23:39:10.748824500 +0100
-@@ -0,0 +1,55 @@
-+/*
-+ * BCM53xx RoboSwitch utility functions
-+ *
-+ * Copyright (C) 2002 Broadcom Corporation
-+ * $Id$
-+ */
-+
-+#ifndef _nvports_h_
-+#define _nvports_h_
-+
-+#define uint32 unsigned long
-+#define uint16 unsigned short
-+#define uint unsigned int
-+#define uint8 unsigned char
-+#define uint64 unsigned long long
-+
-+enum FORCE_PORT {
-+ FORCE_OFF,
-+ FORCE_10H,
-+ FORCE_10F,
-+ FORCE_100H,
-+ FORCE_100F,
-+ FORCE_DOWN,
-+ POWER_OFF
-+};
-+
-+typedef struct _PORT_ATTRIBS
-+{
-+ uint autoneg;
-+ uint force;
-+ uint native;
-+} PORT_ATTRIBS;
-+
-+extern uint
-+nvExistsPortAttrib(char *attrib, uint portno);
-+
-+extern int
-+nvExistsAnyForcePortAttrib(uint portno);
-+
-+extern void
-+nvSetPortAttrib(char *attrib, uint portno);
-+
-+extern void
-+nvUnsetPortAttrib(char *attrib, uint portno);
-+
-+extern void
-+nvUnsetAllForcePortAttrib(uint portno);
-+
-+extern PORT_ATTRIBS
-+nvGetSwitchPortAttribs(uint portno);
-+
-+#endif /* _nvports_h_ */
-+
-+
-+
-diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/osl.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h
---- linux-2.4.32/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/osl.h 2005-12-16 23:39:10.748824500 +0100
-@@ -0,0 +1,42 @@
-+/*
-+ * OS Abstraction Layer
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ * $Id$
-+ */
-+
-+#ifndef _osl_h_
-+#define _osl_h_
-+
-+/* osl handle type forward declaration */
-+typedef struct os_handle osl_t;
-+
-+#if defined(linux)
-+#include <linux_osl.h>
-+#elif defined(NDIS)
-+#include <ndis_osl.h>
-+#elif defined(_CFE_)
-+#include <cfe_osl.h>
-+#elif defined(_HNDRTE_)
-+#include <hndrte_osl.h>
-+#elif defined(_MINOSL_)
-+#include <min_osl.h>
-+#elif PMON
-+#include <pmon_osl.h>
-+#elif defined(MACOSX)
-+#include <macosx_osl.h>
-+#else
-+#error "Unsupported OSL requested"
-+#endif
-+
-+/* handy */
-+#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
-+#define MAXPRIO 7 /* 0-7 */
-+
-+#endif /* _osl_h_ */
-diff -Nur linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h
---- linux-2.4.32/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.4.32-brcm/arch/mips/bcm947xx/include/pcicfg.h 2005-12-16 23:39:10.752824750 +0100
-@@ -0,0 +1,451 @@
-+/*
-+ * pcicfg.h: PCI configuration constants and structures.
-+ *
-+ * Copyright 2005, Broadcom Corporation
-+ * All Rights Reserved.
-+ *
-+ * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
-+ * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
-+ * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
-+ * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
-+ *
-+ * $Id$
-+ */
-+
-+#ifndef _h_pci_
-+#define _h_pci_
-+
-+/* The following inside ifndef's so we don't collide with NTDDK.H */
-+#ifndef PCI_MAX_BUS
-+#define PCI_MAX_BUS 0x100
-+#endif
-+#ifndef PCI_MAX_DEVICES
-+#define PCI_MAX_DEVICES 0x20
-+#endif
-+#ifndef PCI_MAX_FUNCTION
-+#define PCI_MAX_FUNCTION 0x8
-+#endif
-+
-+#ifndef PCI_INVALID_VENDORID
-+#define PCI_INVALID_VENDORID 0xffff
-+#endif
-+#ifndef PCI_INVALID_DEVICEID
-+#define PCI_INVALID_DEVICEID 0xffff
-+#endif
-+
-+
-+/* Convert between bus-slot-function-register and config addresses */
-+
-+#define PCICFG_BUS_SHIFT 16 /* Bus shift */
-+#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
-+#define PCICFG_FUN_SHIFT 8 /* Function shift */
-+#define PCICFG_OFF_SHIFT 0 /* Register shift */
-+
-+#define PCICFG_BUS_MASK 0xff /* Bus mask */
-+#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
-+#define PCICFG_FUN_MASK 7 /* Function mask */
-+#define PCICFG_OFF_MASK 0xff /* Bus mask */
-+
-+#define PCI_CONFIG_ADDR(b, s, f, o) \
-+ ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
-+ | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
-+ | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
-+ | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
-+
-+#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
-+#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
-+#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
-+#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
-+
-+/* PCIE Config space accessing MACROS*/
-+
-+#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
-+#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
-+#define PCIECFG_FUN_SHIFT 16 /* Function shift */
-+#define PCIECFG_OFF_SHIFT 0 /* Register shift */
-+
-+#define PCIECFG_BUS_MASK 0xff /* Bus mask */
-+#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
-+#define PCIECFG_FUN_MASK 7 /* Function mask */
-+#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
-+
-+#define PCIE_CONFIG_ADDR(b, s, f, o) \
-+ ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
-+ | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
-+ | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
-+ | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
-+
-+#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
-+#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
-+#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
-+#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
-+
-+
-+/* The actual config space */
-+
-+#define PCI_BAR_MAX 6
-+
-+#define PCI_ROM_BAR 8
-+
-+#define PCR_RSVDA_MAX 2
-+
-+/* pci config status reg has a bit to indicate that capability ptr is present*/
-+
-+#define PCI_CAPPTR_PRESENT 0x0010
-+
-+typedef struct _pci_config_regs {
-+ unsigned short vendor;
-+ unsigned short device;
-+ unsigned short command;
-+ unsigned short status;
-+ unsigned char rev_id;
-+ unsigned char prog_if;
-+ unsigned char sub_class;
-+ unsigned char base_class;
-+ unsigned char cache_line_size;
-+ unsigned char latency_timer;
-+ unsigned char header_type;
-+ unsigned char bist;
-+ unsigned long base[PCI_BAR_MAX];
-+ unsigned long cardbus_cis;
-+ unsigned short subsys_vendor;
-+ unsigned short subsys_id;
-+ unsigned long baserom;
-+ unsigned long rsvd_a[PCR_RSVDA_MAX];
-+ unsigned char int_line;
-+ unsigned char int_pin;
-+ unsigned char min_gnt;
-+ unsigned char max_lat;
-+ unsigned char dev_dep[192];
-+} pci_config_regs;
-+
-+#define SZPCR (sizeof (pci_config_regs))
-+#define MINSZPCR 64 /* offsetof (dev_dep[0] */
-+
-+/* A structure for the config registers is nice, but in most
-+ * systems the config space is not memory mapped, so we need
-+ * filed offsetts. :-(
-+ */
-+#define PCI_CFG_VID 0
-+#define PCI_CFG_DID 2
-+#define PCI_CFG_CMD 4
-+#define PCI_CFG_STAT 6
-+#define PCI_CFG_REV 8
-+#define PCI_CFG_PROGIF 9
-+#define PCI_CFG_SUBCL 0xa
-+#define PCI_CFG_BASECL 0xb
-+#define PCI_CFG_CLSZ 0xc
-+#define PCI_CFG_LATTIM 0xd
-+#define PCI_CFG_HDR 0xe
-+#define PCI_CFG_BIST 0xf
-+#define PCI_CFG_BAR0 0x10
-+#define PCI_CFG_BAR1 0x14
-+#define PCI_CFG_BAR2 0x18
-+#define PCI_CFG_BAR3 0x1c
-+#define PCI_CFG_BAR4 0x20
-+#define PCI_CFG_BAR5 0x24
-+#define PCI_CFG_CIS 0x28
-+#define PCI_CFG_SVID 0x2c
-+#define PCI_CFG_SSID 0x2e
-+#define PCI_CFG_ROMBAR 0x30
-+#define PCI_CFG_CAPPTR 0x34
-+#define PCI_CFG_INT 0x3c
-+#define PCI_CFG_PIN 0x3d
-+#define PCI_CFG_MINGNT 0x3e
-+#define PCI_CFG_MAXLAT 0x3f
-+
-+/* Classes and subclasses */
-+
-+typedef enum {
-+ PCI_CLASS_OLD = 0,
-+ PCI_CLASS_DASDI,
-+ PCI_CLASS_NET,
-+ PCI_CLASS_DISPLAY,
-+ PCI_CLASS_MMEDIA,
-+ PCI_CLASS_MEMORY,
-+ PCI_CLASS_BRIDGE,
-+ PCI_CLASS_COMM,
-+ PCI_CLASS_BASE,
-+ PCI_CLASS_INPUT,
-+ PCI_CLASS_DOCK,
-+ PCI_CLASS_CPU,
-+ PCI_CLASS_SERIAL,
-+ PCI_CLASS_INTELLIGENT = 0xe,
-+ PCI_CLASS_SATELLITE,
-+ PCI_CLASS_CRYPT,
-+ PCI_CLASS_DSP,
-+ PCI_CLASS_MAX
-+} pci_classes;
-+
-+typedef enum {
-+ PCI_DASDI_SCSI,
-+ PCI_DASDI_IDE,
-+ PCI_DASDI_FLOPPY,
-+ PCI_DASDI_IPI,
-+ PCI_DASDI_RAID,
-+ PCI_DASDI_OTHER = 0x80
-+} pci_dasdi_subclasses;
-+
-+typedef enum {
-+ PCI_NET_ETHER,
-+ PCI_NET_TOKEN,
-+ PCI_NET_FDDI,
-+ PCI_NET_ATM,
-+ PCI_NET_OTHER = 0x80
-+} pci_net_subclasses;
-+
-+typedef enum {
-+ PCI_DISPLAY_VGA,
-+ PCI_DISPLAY_XGA,
-+ PCI_DISPLAY_3D,
-+ PCI_DISPLAY_OTHER = 0x80
-+} pci_display_subclasses;
-+
-+typedef enum {
-+ PCI_MMEDIA_VIDEO,
-+ PCI_MMEDIA_AUDIO,
-+ PCI_MMEDIA_PHONE,
-+ PCI_MEDIA_OTHER = 0x80
-+} pci_mmedia_subclasses;
-+
-+typedef enum {
-+ PCI_MEMORY_RAM,
-+ PCI_MEMORY_FLASH,
-+ PCI_MEMORY_OTHER = 0x80
-+} pci_memory_subclasses;
-+
-+typedef enum {
-+ PCI_BRIDGE_HOST,
-+ PCI_BRIDGE_ISA,
-+ PCI_BRIDGE_EISA,
-+ PCI_BRIDGE_MC,
-+ PCI_BRIDGE_PCI,
-+ PCI_BRIDGE_PCMCIA,
-+ PCI_BRIDGE_NUBUS,
-+ PCI_BRIDGE_CARDBUS,
-+ PCI_BRIDGE_RACEWAY,
-+ PCI_BRIDGE_OTHER = 0x80
-+} pci_bridge_subclasses;
-+
-+typedef enum {
-+ PCI_COMM_UART,
-+ PCI_COMM_PARALLEL,
-+ PCI_COMM_MULTIUART,
-+ PCI_COMM_MODEM,
-+ PCI_COMM_OTHER = 0x80
-+} pci_comm_subclasses;
-+
-+typedef enum {
-+ PCI_BASE_PIC,
-+ PCI_BASE_DMA,
-+ PCI_BASE_TIMER,
-+ PCI_BASE_RTC,
-+ PCI_BASE_PCI_HOTPLUG,
-+ PCI_BASE_OTHER = 0x80
-+} pci_base_subclasses;
-+
-+typedef enum {
-+ PCI_INPUT_KBD,
-+ PCI_INPUT_PEN,
-+ PCI_INPUT_MOUSE,
-+ PCI_INPUT_SCANNER,
-+ PCI_INPUT_GAMEPORT,
-+ PCI_INPUT_OTHER = 0x80
-+} pci_input_subclasses;
-+
-+typedef enum {
-+ PCI_DOCK_GENERIC,
-+ PCI_DOCK_OTHER = 0x80
-+} pci_dock_subclasses;
-+
-+typedef enum {
-+ PCI_CPU_386,
-+ PCI_CPU_486,
-+ PCI_CPU_PENTIUM,
-+ PCI_CPU_ALPHA = 0x10,
-+ PCI_CPU_POWERPC = 0x20,
-+ PCI_CPU_MIPS = 0x30,
-+ PCI_CPU_COPROC = 0x40,
-+ PCI_CPU_OTHER = 0x80
-+} pci_cpu_subclasses;
-+
-+typedef enum {
-+ PCI_SERIAL_IEEE1394,
-+ PCI_SERIAL_ACCESS,
-+ PCI_SERIAL_SSA,
-+ PCI_SERIAL_USB,
-+ PCI_SERIAL_FIBER,
-+ PCI_SERIAL_SMBUS,
-+ PCI_SERIAL_OTHER = 0x80
-+} pci_serial_subclasses;
-+
-+typedef enum {
-+ PCI_INTELLIGENT_I2O,
-+} pci_intelligent_subclasses;
-+
-+typedef enum {
-+ PCI_SATELLITE_TV,
-+ PCI_SATELLITE_AUDIO,
-+ PCI_SATELLITE_VOICE,
-+ PCI_SATELLITE_DATA,
-+ PCI_SATELLITE_OTHER = 0x80
-+} pci_satellite_subclasses;
-+
-+typedef enum {
-+ PCI_CRYPT_NETWORK,
-+ PCI_CRYPT_ENTERTAINMENT,
-+ PCI_CRYPT_OTHER = 0x80
-+} pci_crypt_subclasses;
-+
-+typedef enum {
-+ PCI_DSP_DPIO,
-+ PCI_DSP_OTHER = 0x80
-+} pci_dsp_subclasses;
-+
-+/* Header types */
-+typedef enum {
-+ PCI_HEADER_NORMAL,
-+ PCI_HEADER_BRIDGE,
-+ PCI_HEADER_CARDBUS
-+} pci_header_types;
-+
-+
-+/* Overlay for a PCI-to-PCI bridge */
-+
-+#define PPB_RSVDA_MAX 2
-+#define PPB_RSVDD_MAX 8
-+
-+typedef struct _ppb_config_regs {
-+ unsigned short vendor;
-+ unsigned short device;
-+ unsigned short command;
-+ unsigned short status;
-+ unsigned char rev_id;
-+ unsigned char prog_if;
-+ unsigned char sub_class;
-+ unsigned char base_class;
-+ unsigned char cache_line_size;
-+ unsigned char latency_timer;
-+ unsigned char header_type;
-+ unsigned char bist;
-+ unsigned long rsvd_a[PPB_RSVDA_MAX];
-+ unsigned char prim_bus;
-+ unsigned char sec_bus;
-+ unsigned char sub_bus;
-+ unsigned char sec_lat;
-+ unsigned char io_base;
-+ unsigned char io_lim;
-+ unsigned short sec_status;
-+ unsigned short mem_base;
-+ unsigned short mem_lim;
-+ unsigned short pf_mem_base;
-+ unsigned short pf_mem_lim;
-+ unsigned long pf_mem_base_hi;
-+ unsigned long pf_mem_lim_hi;
-+ unsigned short io_base_hi;
-+ unsigned short io_lim_hi;
-+ unsigned short subsys_vendor;
-+ unsigned short subsys_id;
-+ unsigned long rsvd_b;
-+ unsigned char rsvd_c;
-+ unsigned char int_pin;
-+ unsigned short bridge_ctrl;
-+ unsigned char chip_ctrl;
-+ unsigned char diag_ctrl;
-+ unsigned short arb_ctrl;
-+ unsigned long rsvd_d[PPB_RSVDD_MAX];
-+ unsigned char dev_dep[192];
-+} ppb_config_regs;
-+
-+
-+/* PCI CAPABILITY DEFINES */
-+#define PCI_CAP_POWERMGMTCAP_ID 0x01
-+#define PCI_CAP_MSICAP_ID 0x05
-+#define PCI_CAP_PCIECAP_ID 0x10