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powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA
authorTimur Tabi <timur@freescale.com>
Thu, 14 Apr 2011 20:37:06 +0000 (15:37 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Fri, 29 Apr 2011 03:09:23 +0000 (22:09 -0500)
commitf68d3063491442ca5d871d3019a9d3f195873ed7
tree10ebc71b9adaee748e9254e1ebe3338b2392ec21tree | snapshot
parent7d6d9ba9d0cb0bb2fefc4ce16c191c1bbad7b656commit | diff
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA

Part of the SERDES9 erratum work-around is to set some bits in the SerDes
TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA.  The
current code does this only for XAUI, so extend it to the other protocols.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c diff | blob | history
arch/powerpc/include/asm/immap_85xx.h diff | blob | history
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