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(parent: 56747bf) | patch
arch/arm: add SEC JR0 offset
authorAlex Porosanu <alexandru.porosanu@freescale.com>
Fri, 29 Apr 2016 12:17:58 +0000 (15:17 +0300)
committerYork Sun <york.sun@nxp.com>
Wed, 18 May 2016 15:51:46 +0000 (08:51 -0700)
commite99d7193593cf6331ea04cd394a9a4cf18886ef0
treea187ad9403f8e304c9dd954aec3a8aad51557e08tree | snapshot
parent56747bfdbd6f2c5bc391d0c9d5eb20a6a2d50505commit | diff
arch/arm: add SEC JR0 offset

Freescale PPC SoCs do not hard-code security engine's Job Ring 0
address, rather a define is used. This patch adds the same
functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts)

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h diff | blob | history
arch/arm/include/asm/arch-ls102xa/config.h diff | blob | history
arch/arm/include/asm/arch-mx6/imx-regs.h diff | blob | history
arch/arm/include/asm/arch-mx7/imx-regs.h diff | blob | history
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