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x86: braswell: Add microcode for B0/C0/D0 stepping SoC
authorBin Meng <bmeng.cn@gmail.com>
Wed, 16 Aug 2017 05:41:59 +0000 (22:41 -0700)
committerBin Meng <bmeng.cn@gmail.com>
Sat, 16 Sep 2017 06:57:44 +0000 (14:57 +0800)
commite61a2687b3ed9661755a33146530a51320cdd76b
tree68ae47104692f13308299ed9f046ef3c9c94d8f3tree | snapshot
parentde9ac9a1b9c0899d05d582917330092d577d5ebecommit | diff
x86: braswell: Add microcode for B0/C0/D0 stepping SoC

This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/x86/dts/microcode/m01406c2220.dtsi [new file with mode: 0644] blob
arch/x86/dts/microcode/m01406c3363.dtsi [new file with mode: 0644] blob
arch/x86/dts/microcode/m01406c440a.dtsi [new file with mode: 0644] blob
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