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(parent: fdf02a3) | patch
spi: cadence_qspi_apb: Support 32 bit AHB address
authorVignesh R <vigneshr@ti.com>
Wed, 6 Jul 2016 04:50:55 +0000 (10:20 +0530)
committerJagan Teki <jteki@openedev.com>
Sat, 9 Jul 2016 14:46:32 +0000 (20:16 +0530)
commitdac3bf20fb2c9b03476be0d73db620f62ab3cee1
treebaae7a2ca8cd9342f5879bcfca6e20495037a455tree | snapshot
parentfdf02a36c52cb96717b64113775c4251ecd49596commit | diff
spi: cadence_qspi_apb: Support 32 bit AHB address

AHB address can be as long as 32 bit, hence remove the
CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT
and read as u32 value, it anyway does not make sense to mask upper bits.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
drivers/spi/cadence_qspi_apb.c diff | blob | history
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