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Tegra: Fix MSELECT clock divisors for T30/T114.
authorTom Warren <twarren@nvidia.com>
Wed, 3 Apr 2013 21:39:30 +0000 (14:39 -0700)
committerTom Warren <twarren@nvidia.com>
Mon, 15 Apr 2013 18:01:38 +0000 (11:01 -0700)
commitd94c2dbd0a55d742ab6ed9bd0c51b27ceed4084e
tree5bdef44cb41f3818fec6d5741654bba1348ef19atree | snapshot
parentb40f734af9fdc47a0993f1f94f32d40a86f30587commit | diff
Tegra: Fix MSELECT clock divisors for T30/T114.

A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
arch/arm/cpu/arm720t/tegra114/cpu.c diff | blob | history
arch/arm/cpu/arm720t/tegra30/cpu.c diff | blob | history
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