drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
authorShengzhou Liu <Shengzhou.Liu@nxp.com>
Wed, 4 May 2016 02:20:21 +0000 (10:20 +0800)
committerYork Sun <york.sun@nxp.com>
Fri, 3 Jun 2016 21:06:35 +0000 (14:06 -0700)
commitd8e5163ad81a2810c66a9a98e5111769378f5f5f
tree0bc10413b7d7ef030566206bba5ff0df5b2046c6
parent8b528709c5bba6a8d0ec83b20545bbd75f082704
drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
drivers/ddr/fsl/ctrl_regs.c