git.librecmc.org Git - oweals/u-boot.git/commit

author	Parthiban Nallathambi <parthitce@gmail.com>
	Wed, 17 Apr 2019 22:04:09 +0000 (00:04 +0200)
committer	Stefano Babic <sbabic@denx.de>
	Thu, 25 Apr 2019 17:16:24 +0000 (19:16 +0200)
commit	d8d33b6d4dd2ecd2ea2a3d3ece9e22528d8fd15c
tree	9e5870f0b8e7e6e24d71e15dc8316d35e555d21f	tree \| snapshot
parent	b3cf86c86bf00d7d3ee9bc7ecb0819105b641c89	commit \| diff

imx: Add variscite DART-6UL Evaluation Kit

Port for the DART-6UL Evaluation Kit SBC. Based on the variscite
DART-6UL iMX6ULL SoM.

CPU:   Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 43C
Reset cause: POR
Model: Variscite DART-6UL Evaluation Kit
Board: Variscite DART-6UL Evaluation Kit
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial@02020000
Out:   serial@02020000
Err:   serial@02020000
Net:   FEC0

Working:
- Eth0
- i2c
- MMC/SD
- eMMC
- USB host
- UART 1

Note: LCDIF porting needs DM_VIDEO
https://lists.denx.de/pipermail/u-boot/2019-April/365506.html

Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>

13 files changed:

arch/arm/Kconfig		diff \| blob \| history
arch/arm/dts/Makefile		diff \| blob \| history
arch/arm/dts/imx6ull-dart-6ul.dts	[new file with mode: 0644]	blob
arch/arm/dts/imx6ull-dart-6ul.dtsi	[new file with mode: 0644]	blob
arch/arm/mach-imx/mx6/Kconfig		diff \| blob \| history
board/variscite/dart_6ul/Kconfig	[new file with mode: 0644]	blob
board/variscite/dart_6ul/MAINTAINERS	[new file with mode: 0644]	blob
board/variscite/dart_6ul/Makefile	[new file with mode: 0644]	blob
board/variscite/dart_6ul/README	[new file with mode: 0644]	blob
board/variscite/dart_6ul/dart_6ul.c	[new file with mode: 0644]	blob
board/variscite/dart_6ul/spl.c	[new file with mode: 0644]	blob
configs/variscite_dart6ul_defconfig	[new file with mode: 0644]	blob
include/configs/dart_6ul.h	[new file with mode: 0644]	blob

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