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(parent: 3db0bef) | patch
Empirically set cpo and clk_adjust for mpc85xx DDR2 support
authorHaiying Wang <Haiying.Wang@freescale.com>
Tue, 19 Jun 2007 18:18:32 +0000 (14:18 -0400)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 14 Aug 2007 06:45:51 +0000 (01:45 -0500)
commitd111d6382c99fdea08c2312eeeae8786945e189a
tree689badef14549bda5ac780242e9e2a6f8047a522tree | snapshot
parent3db0bef59eab1155801618cef5c481e97553b597commit | diff
Empirically set cpo and clk_adjust for mpc85xx DDR2 support

This patch is against u-boot-mpc85xx.git of www.denx.com

Setting cpo to 0x9 for frequencies higher than 333MHz is verified on
both MPC8548CDS board and MPC8568MDS board, especially for supporting
533MHz DDR2.

Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for
DDR2 on all current board versions especially ver 1.92 or later to bring
up.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
cpu/mpc85xx/spd_sdram.c diff | blob | history
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