clk: clk_meson: Add mux and div support for reparent and rate setting
authorNeil Armstrong <narmstrong@baylibre.com>
Mon, 6 Aug 2018 12:49:20 +0000 (14:49 +0200)
committerTom Rini <trini@konsulko.com>
Tue, 11 Sep 2018 00:48:17 +0000 (20:48 -0400)
commitc8e570167f8a2eadbd5f3c7a2b38a9e3796cea19
tree9062d050420c614bce2c23d6797b60c0143d2d29
parent8d5579ceff2403d78a7fed1e06c5f003b3bca12a
clk: clk_meson: Add mux and div support for reparent and rate setting

This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenting for muxes
- Clock rate setting through generic dividers without reparenting

Support is only added to the Composite VPU and VAPB clocks in order
to support the Video Processing Unit Power Domain clock setup.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
drivers/clk/clk_meson.c