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(parent: dc774e6) | patch
ARM: uniphier: fix SSCPLL init code for LD11 SoC
authorDai Okamura <okamura.dai@socionext.com>
Wed, 6 Dec 2017 05:16:32 +0000 (14:16 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Mon, 11 Dec 2017 15:36:11 +0000 (00:36 +0900)
commitc30c44e799e1f7d5184c487809edbd612705ba5c
tree211962f11fa2e3f0793123c8a802584c55fcf7e8tree | snapshot
parentdc774e69bb72a3d8ff4c2af7a280a655f395530bcommit | diff
ARM: uniphier: fix SSCPLL init code for LD11 SoC

Commit 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
missed to write the computed value to the SSCPLLCTRL2 register.

Fixes: 682e09ff9f35 ("ARM: uniphier: add PLL init code for LD20 SoC")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/mach-uniphier/clk/pll-base-ld20.c diff | blob | history
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