rockchip: rk3036: Add core Soc start-up code
authorhuang lin <hl@rock-chips.com>
Tue, 17 Nov 2015 06:20:27 +0000 (14:20 +0800)
committerSimon Glass <sjg@chromium.org>
Tue, 1 Dec 2015 15:07:22 +0000 (08:07 -0700)
commitbe1d5e0388d2e506d875d4b984485526bdf3197f
tree8118089e14f8848081646826253e8ada3d9379ef
parent53c45f0ca27cbf6acd840e87beaa1ba1be74399b
rockchip: rk3036: Add core Soc start-up code

rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/Makefile
arch/arm/mach-rockchip/board.c
arch/arm/mach-rockchip/rk3036-board-spl.c [new file with mode: 0644]
arch/arm/mach-rockchip/rk3036/Kconfig [new file with mode: 0644]
arch/arm/mach-rockchip/rk3036/Makefile
arch/arm/mach-rockchip/rk3036/save_boot_param.S [new file with mode: 0644]
include/configs/rk3036_common.h [new file with mode: 0644]