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(parent: be0be37) | patch
Fix wrong DPLL2 in SRIF area register definitions for QCA953x
authorPiotr Dymacz <pepe2k@gmail.com>
Thu, 10 Dec 2015 13:54:52 +0000 (14:54 +0100)
committerPiotr Dymacz <pepe2k@gmail.com>
Thu, 10 Dec 2015 13:54:52 +0000 (14:54 +0100)
commitbd9144fe3454f6bc6589401e569cf4dc13e8d6bc
tree756b1957a190fa047c34a51eeea691a8b117fdd2tree | snapshot
parentbe0be37a8eb98cde4dbcad40ac815940285649a2commit | diff
Fix wrong DPLL2 in SRIF area register definitions for QCA953x

As usual... you should not trust QC/A datasheets!
They are so buggy and contain lot of copy&paste mistakes.

DPLL2 register in SRIF for QCA953x seems to be totally different
than in other QCA95xx WiSOCs. Happily, definitions in original code
from SDK seem to be correct, so we will use it instead.

Clock settings based on setting default and SRIF PLL was confirmed on scope.
u-boot/include/soc/qca_soc_common.h diff | blob | history
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