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(parent: 60082d3) | patch
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset
authorMarek Vasut <marex@denx.de>
Tue, 8 May 2018 16:44:43 +0000 (18:44 +0200)
committerMarek Vasut <marex@denx.de>
Sat, 9 Mar 2019 16:59:14 +0000 (17:59 +0100)
commitbd6363a7b77f0a5737b736f80179b6f53ef2cf7c
tree1da56b2c374dbf3a72806923ffcd040b510ca95btree | snapshot
parent60082d3b3ff17fc0c5ae6c1cdd176219554ed61fcommit | diff
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset

The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
include/configs/socfpga_common.h diff | blob | history
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