clk: stm32mp1: correctly handle Clock Spreading Generator
authorPatrick Delaunay <patrick.delaunay@st.com>
Wed, 30 Jan 2019 12:07:06 +0000 (13:07 +0100)
committerTom Rini <trini@konsulko.com>
Sat, 9 Feb 2019 12:50:57 +0000 (07:50 -0500)
commitbbd108a08225b1239b1ec1c10e8131fba6a3a95a
tree3324114ed3c850227bebde0f28d258b303028b50
parente74b74c52876d776dda7a7ee5e2a8d555eaa5c4f
clk: stm32mp1: correctly handle Clock Spreading Generator

To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
doc/device-tree-bindings/clock/st,stm32mp1.txt
drivers/clk/clk_stm32mp1.c