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(parent: 8c9ce08) | patch
ram: stm32mp1_ddr: fix self refresh disable during DQS training
authorPatrick Delaunay <patrick.delaunay@st.com>
Fri, 6 Mar 2020 10:14:09 +0000 (11:14 +0100)
committerPatrick Delaunay <patrick.delaunay@st.com>
Tue, 24 Mar 2020 13:23:18 +0000 (14:23 +0100)
commitb604a41c6bcfb6273e7478089ff3e7b65e233645
treedc7f3cd77c1fecd3024f0eeb51a281a007fd530etree | snapshot
parent8c9ce0807545976c4080621be80dfb02b4ead400commit | diff
ram: stm32mp1_ddr: fix self refresh disable during DQS training

DDRCTRL_PWRCTL.SELFREF_EN needs to be reset before DQS training step, not
to enter in self refresh mode during the execution of this phase.
Depending on settings, it can be set after the DQS training.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrice Chotard <patrice.chotard@st.com>
drivers/ram/stm32mp1/stm32mp1_ddr.c diff | blob | history
drivers/ram/stm32mp1/stm32mp1_ddr_regs.h diff | blob | history
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