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(parent: e57f0fa) | patch
85xx: Add CPU 2 errata workaround to all 8548 boards
authorPeter Tyser <ptyser@xes-inc.com>
Tue, 11 Nov 2008 16:17:10 +0000 (10:17 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Thu, 4 Dec 2008 04:46:42 +0000 (22:46 -0600)
commita2cd50ed6ef0ac6b127b3d6db756979a8336718d
treea8064eb08a501fdecadfb50af56f646c90be0f3atree | snapshot
parente57f0fa1333cdf3ca36110aac2900712a5f82976commit | diff
85xx: Add CPU 2 errata workaround to all 8548 boards

All mpc8548-based boards should implement the suggested workaround
to CPU 2 errata. Without the workaround, its possible for the
8548's core to hang while executing a msync or mbar 0 instruction
and a snoopable transaction from an I/O master tagged to make
quick forward progress is present.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
board/freescale/mpc8548cds/mpc8548cds.c diff | blob | history
board/sbc8548/sbc8548.c diff | blob | history
cpu/mpc85xx/cpu_init.c diff | blob | history
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