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(parent: 485c13c) | patch
armv8: lsch3: Add serdes and DDR voltage setup
authorRajesh Bhagat <rajesh.bhagat@nxp.com>
Wed, 17 Jan 2018 10:43:00 +0000 (16:13 +0530)
committerYork Sun <york.sun@nxp.com>
Tue, 23 Jan 2018 19:18:12 +0000 (11:18 -0800)
commita1f95ff7d7bae4d4dac59aa6d53f3625af43765e
treed975cb046e2fab6fb8aa8c25049744c7ffd85484tree | snapshot
parent485c13c7536731991c59f7b3432bc33c9dafb0f0commit | diff
armv8: lsch3: Add serdes and DDR voltage setup

Adds SERDES voltage and reset SERDES lanes API and makes
enable/disable DDR controller support 0.9V API common.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c diff | blob | history
arch/arm/cpu/armv8/fsl-layerscape/soc.c diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/soc.h diff | blob | history
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