rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
authorPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Thu, 22 Jun 2017 22:01:10 +0000 (00:01 +0200)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sun, 13 Aug 2017 15:12:32 +0000 (17:12 +0200)
commita00dfa042d3eecbe96308d87f38710e79a29e00c
tree9494c847f063d2baf3c4d94bac4cb0b7e683d566
parent4bebf94e8544399d040e0dc46d7ec72d64853237
rockchip: clk: rk3368: implement DPLL (DRAM PLL) support

To implement a TPL stage (incl. its DRAM controller setup) for the
RK3368, we'll want to configure the DPLL (DRAM PLL).

This commit implements setting the DPLL (CLK_DDR) and provides PLL
configuration details for the common DRAM operating speeds found on
RK3368 boards.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/clk/rockchip/clk_rk3368.c