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mx7ulp: Select the SCG1 APLL PFD as a system clock source
authorYe Li <ye.li@nxp.com>
Wed, 15 May 2019 09:56:59 +0000 (09:56 +0000)
committerStefano Babic <sbabic@denx.de>
Fri, 19 Jul 2019 18:14:50 +0000 (20:14 +0200)
commit9c1563e3fd24ca7161c089dfd999d031f95094de
tree2427c80f845acaaaca1c198f46f06fa63c89a0c2tree | snapshot
parent285aea01d2f9398b9c127c7a7fbaa401adf6969fcommit | diff
mx7ulp: Select the SCG1 APLL PFD as a system clock source

Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
board/freescale/mx7ulp_evk/imximage.cfg diff | blob | history
board/freescale/mx7ulp_evk/plugin.S diff | blob | history
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