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(parent: 0691484) | patch
arm64: Disable TTBR1 maps in EL1
authorAlexander Graf <agraf@suse.de>
Fri, 4 Mar 2016 00:09:46 +0000 (01:09 +0100)
committerTom Rini <trini@konsulko.com>
Tue, 15 Mar 2016 19:13:00 +0000 (15:13 -0400)
commit9bb367a590feac21d674e4d2cee77702d4774819
tree03ded1f537f9b0c2857f6efe1de441635206466btree | snapshot
parent0691484ac1efb1981dfd1b38df9646128bafff32commit | diff
arm64: Disable TTBR1 maps in EL1

When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).

In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.

Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
arch/arm/cpu/armv8/cache_v8.c diff | blob | history
arch/arm/include/asm/armv8/mmu.h diff | blob | history
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