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(parent: 9ba379a) | patch
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
authorBryan Brinsko <bryan.brinsko@rockwellcollins.com>
Tue, 24 Mar 2015 16:25:12 +0000 (11:25 -0500)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Thu, 16 Apr 2015 12:59:33 +0000 (14:59 +0200)
commit97840b5d1fe0960134c3553a9d9d1c1cd1be784d
tree3ae40c9ca7eceb5306544d318e38e6dad6dcedb2tree | snapshot
parent9ba379ade789e41cc4132d622315f3f021a47b9bcommit | diff
ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching

The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
arch/arm/include/asm/system.h diff | blob | history
arch/arm/lib/cache-cp15.c diff | blob | history
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