ARM: DRA7xx: clocks: Update PLL values
authorLokesh Vutla <lokeshvutla@ti.com>
Thu, 30 May 2013 03:19:38 +0000 (03:19 +0000)
committerTom Rini <trini@ti.com>
Mon, 10 Jun 2013 12:43:10 +0000 (08:43 -0400)
commit97405d843ece2a53e67b801e02ee42005d26e172
tree13c4b866c44ebbbb7033f7490921fcb6dffa6004
parent7f36c88f64ee1affd4db78b2c2f4a616abceb84c
ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
arch/arm/cpu/armv7/omap-common/clocks-common.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/prcm-regs.c
arch/arm/include/asm/arch-omap4/clock.h
arch/arm/include/asm/arch-omap5/clock.h
arch/arm/include/asm/omap_common.h
include/configs/dra7xx_evm.h