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(parent: 85e7c7a) | patch
Tweak DDR ECC error counter
authorAndy Fleming <afleming@freescale.com>
Sat, 24 Feb 2007 07:16:45 +0000 (01:16 -0600)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 24 Apr 2007 00:58:28 +0000 (19:58 -0500)
commit9343dbf85bc03033f2102d8e8543567c2c1ad2d2
tree94edfc80e63eb36793f6feed2c46339e0cfb9ccetree | snapshot
parent85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4bcommit | diff
Tweak DDR ECC error counter

Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
cpu/mpc85xx/spd_sdram.c diff | blob | history
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