driver/ddr: Add support for setting timing in hws_topology_map
authorMarek BehĂșn <marek.behun@nic.cz>
Fri, 9 Jun 2017 17:28:40 +0000 (19:28 +0200)
committerStefan Roese <sr@denx.de>
Wed, 12 Jul 2017 04:56:48 +0000 (06:56 +0200)
commit90bcc3d38d2b1159e1b80da050f6163e5c3f575d
tree89f960d9e430834eae7769c59640c11d7db926a6
parent8d3a25685e4aac7070365a2b3c53c2c81b27930f
driver/ddr: Add support for setting timing in hws_topology_map

The DDR3 training code for Marvell A38X currently computes 1t timing
when given board topology map of the Turris Omnia, but Omnia needs 2t.

This patch adds support for enforcing the 2t timing in struct
hws_topology_map, through a new enum hws_timing, which can assume
following values:
  HWS_TIM_DEFAULT - default behaviour, compute whether to enable 2t
                    from the number of CSs
  HWS_TIM_1T      - enforce 1t
  HWS_TIM_2T      - enforce 2t

This patch also sets all the board topology maps (db-88f6820-amc,
db-88f6820-gp, controlcenterdc and clearfog) to have timing set to
HWS_TIM_DEFAULT.

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
board/Marvell/db-88f6820-amc/db-88f6820-amc.c
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
board/gdsys/a38x/controlcenterdc.c
board/solidrun/clearfog/clearfog.c
drivers/ddr/marvell/a38x/ddr3_training.c
drivers/ddr/marvell/a38x/ddr_topology_def.h