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(parent: 2efd27f) | patch
ddr: marvell: update additional ODT setting
authorChris Packham <judge.packham@gmail.com>
Thu, 18 Jan 2018 04:16:09 +0000 (17:16 +1300)
committerStefan Roese <sr@denx.de>
Fri, 19 Jan 2018 15:30:29 +0000 (16:30 +0100)
commit8bddf678dbe3c766d4f1c242cda3b9e3ed9e2425
tree79398711daa0e2f0dacbef1b99943e9519fbbaa2tree | snapshot
parent2efd27f76ae027deba2a1aaadeece80362ba6297commit | diff
ddr: marvell: update additional ODT setting

The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f
instead of 0xf. Rather than checking the read sample delay for all DDR
chip selects use the values for the chip selects that are actually
configured. Finally continue searching for the max_phase value even if the
current read_sample is the same as the max_read_sample.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c diff | blob | history
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