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(parent: 502a710) | patch
mx6: clock: Fix the calculation of PLL_ENET frequency
authorFabio Estevam <fabio.estevam@freescale.com>
Tue, 3 Dec 2013 20:26:13 +0000 (18:26 -0200)
committerStefano Babic <sbabic@denx.de>
Tue, 17 Dec 2013 17:38:42 +0000 (18:38 +0100)
commit89cfd0f5757413093ad179478b80367d7bd34ecc
tree9d046959fc79a25c3d6fc3172854027bc8a72320tree | snapshot
parent502a710f5b54bbb966db4c4516abf5d82f46dd47commit | diff
mx6: clock: Fix the calculation of PLL_ENET frequency

According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:

"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"

Current logic does not handle the 25MHz case correctly, so fix it.

Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
arch/arm/cpu/armv7/mx6/clock.c diff | blob | history
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