ddr: socfpga: Clean up ddr_setup()
authorMarek Vasut <marex@denx.de>
Sat, 9 Mar 2019 20:58:09 +0000 (21:58 +0100)
committerMarek Vasut <marex@denx.de>
Sat, 9 Mar 2019 22:25:19 +0000 (23:25 +0100)
commit88c3bb49e1bf2b808cbad1fbdeda09480ae580a7
tree65cb29a0d376e6842cc5e00d230d27d14b741300
parent8297dd1d934281175ffa8646a2e3200755402db5
ddr: socfpga: Clean up ddr_setup()

Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
drivers/ddr/altera/sdram_arria10.c